Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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Fast Single-Phase All Digital Phase-Locked Loop for Grid Synchronization under Distorted Grid Conditions

  • Zhang, Peiyong (College of Electrical Engineering, Zhejiang University) ;
  • Fang, Haixia (College of Electrical Engineering, Zhejiang University) ;
  • Li, Yike (College of Electrical Engineering, Zhejiang University) ;
  • Feng, Chenhui (College of Physics and Information Engineering, Fuzhou University)
  • Received : 2017.07.16
  • Accepted : 2018.04.06
  • Published : 2018.09.20
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Abstract

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

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References

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