• Journal of Electrical Engineering and Technology
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• 제6권5호
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1987년도 학술발표회 논문집
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• pp.79-81
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• 1987

In this paper we propose a fast adaptive least squares algorithm for linear phase FIR filters. The algorithm requires 10m multiplications per data point where m is the filter order. Both linear phase cases with constant phase delay and constant group delay are examined. Simulation results demonstrate that the proeposed algorithm is superior to the LMS gradient algorithm and the averaging scheme used for the modified fast Kalman algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.172-177
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• 1988

In this paper, a new fast algorithm of FIR least squares filter with linear phase is presented. The general unknown statistics case is considered, whereby only sample records of the data are available. Taking advantage of the near-to-Toeplitz+Hankel structure of the resulting normal equation, a fast algorithm which gurantees the linear phase constraint, is developed that recursively produces the filter coefficient of linear phase FIR filter for a single block of data.

• Journal of Power Electronics
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• 제16권4호
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• pp.1513-1525
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• 2016

Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.387-390
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• 2012

본 논문에서는 임베디드 리눅스 기반 단말기의 빠른 부팅 개선을 위해 부팅 과정을 부트로더, 커널, 파일 시스템, 초기화 스크립트, 공유 라이브러리, 응용 프로그램 등 6가지 단계로 나누었다. 빠른 부팅 개선을 위해 전원인가 시 최초로 실행되는 부트로더 단계와 초기화 스크립트 단계에 적용했다. 부트로더 단계에서 입력 대기 시간 제거, 불필요한 초기화 루틴제거, 커널 이미지 비압축 로드, 최적화된 복사 루틴 사용 등을 적용하여 부팅 개선을 했다. 또한 초기화 스크립트 단계에서 이진화 기반 스크립트 대체 기술 사용, init 프로세스 경량화 등을 적용하여 부팅 개선을 했다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 한국운동역학회지
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• 제28권2호
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• pp.93-100
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• 2018

Objective: The purpose of this study is to analyze the kinematic characteristics of the national speed skaters in the curve phase of 500-m race. Method: Seven national skaters participated in the study. Race images were acquired using a high - speed camera, and the three-dimensional motion was analyzed. Results: For skaters, whose average velocity in the curve phase is high, the velocity of entry into the straight phase was also fast. The fast skaters showed a larger maximum angle of extension of the knee joints than the relatively slow skaters, and the trunk ROM was smaller. Fast skaters tended to match the timing of the movement of the lower limb with the pelvis, while slow skaters tended to rotate the left pelvis backward. The velocity of the curve phase did not show a clear relationship with stroke time, average trunk angle, and lap time. Conclusion: It is important to skate close to the inner line, keep the trunk ROM below 10 degrees, extend the knee angle to over 160 degrees, and match the movement of the pelvis and lower limb to accelerate in the curve phase. The average velocity of the curves was fast for many athletes, but the competition rankings were low. Therefore, it is possible to improve the performance by optimizing the start technique, the running characteristics of the straight phase, and the physical factors.

• 한국정보통신학회논문지
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• 제9권3호
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• pp.582-586
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• 2005

본 논문은 locking 상태에 따라서 루프대역폭이 변화하는 Phase Locked Loop (PLL)의 구조를 제안하였다. 제안한 PLL은 기본적인 PLL 블록과 NOR Gate, Inverter, Capacitor, 그리고 Schmitt trigger로 이루어진 Locking Status Indicator(LSI) 블록으로 구성되었다. LSI는 Loop Fille.(LF)에 공급되는 전류와 저항 값을 locking 상태에 따라 변화시켜서 unlock이 되면 넓은 루프대역폭 가지는 PLL로, lock이 되면 좁은 루프대역폭을 가지는 PLL로 동작하도록 한다. 이러한 구조의 PLL은 짧은 locking 시간과 저 잡음의 특성을 동시에 만족시킬 수 있다. 제안된 PLL은 Hynix CMOS $0.35{\mu}m$ 공정으로 Hspice 시뮬레이션 하였으며 40us의 짧은 locking 시간과 -76.1dBc 크기의 spur를 가진다.

• 전기전자학회논문지
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• 제20권3호
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• pp.314-317
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• 2016

최근 휴대용 기기의 수요가 증가함에 따라 배터리 사용시간을 최대화하기 위한 노력이 진행되고 있다. 본 논문에서는 빠른 과도 응답을 갖는 멀티페이스 벅 변환기를 제안한다. 멀티페이스 벅 변환기는 리플 상쇄 효과가 있기 때문에 작은 크기의 출력 캐패시터를 사용할 수 있고, 더 적은 인덕턴스를 갖는 인덕터의 사용이 가능하다. 휴대용 기기가 대기 모드에서 활성 모드로 빠르게 변할 수 있도록 4-페이스 구조로 설계하여 빠른 과도 응답을 갖게 하였다. 사용된 공정은 Hynix 0.18um CMOS 공정을 통해 제작되었고 공급전압 범위는 2.7~3.3V 이며, 최대 부하 전류는 500mA, settling time은 14us이다.

• 한국건설관리학회:학술대회논문집
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• 한국건설관리학회 2008년도 정기학술발표대회 논문집
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• pp.5-12
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• 2008

양산 부산대학교병원 건립공사는 종합병원 의료타운 신축 프로젝트이다. 계획단계부터 건설사업관리자(CMr)가 참가하여 설계 시공일괄사업자를 선정한 후, 실시설계 진행과정을 거쳐 시공단계, 시공이후단계에 이르기까지 프로젝트의 모든 단계에 건설사업관리(CM) 업무를 일관적으로 적용한 사례이다. 또한 설계와 시공의 추진에 Fast Track을 도입하여 공기단축에 성공한 것에 그 의미를 찾을 수 있다. 본 사례는 설계 이전단계에 설계시공일관업체를 선정하였으며, Fast Track수법의 적용을 염두에 둔 설계 및 공사일정계획, 설계단계의 설계관리, Fast Track에 입각한 단계별 공사발주 및 계약관리, 기본설계 실시설계단계의 VE 수행, 시공단계에서의 설계변경 관리, 시공 후 유지관리 단계의 운용관리 등 건설사업관리 업무가 모든 단계에서 다각적으로 제공되었다. 본 보고에서는 상기와 같은 건설사업관리 적용상의 과제와 개선방향, 특히 설계 시공일괄사업에서 효율적으로 CM 업무를 수행할 수 있는 방안을 제시하여, 초대형 턴키(Turnkey) 프로젝트의 CM적용에 기여하고자 한다.