• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Journal of Information Processing Systems
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• v.14 no.2
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• Journal of the Korean Chemical Society
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• v.35 no.6
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• pp.713-719
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• 1991

Electrochemical impedance measurement system using Fourier transform was constructed in the range of the frequencies up to 100 kHz. This system consists of pseudo-random noise generator, specially designed potentiostat, fast data acquisition system, system controller, and computer interface. The performance of the constructed system was found to be almost same as the commercially available system using lock-in amplifier. Measuring time was significantly reduced because the minimum time for the measurement depended on one cycle of the lowest frequency used. It would be possible to study time-varying electrochemical impedance systems such as the initial stages of corrosion processes using this system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• The KIPS Transactions:PartD
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• v.10D no.2
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• pp.195-210
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• 2003

In this paper, we propose an enhanced concurrency control algorithm that maximizes the concurrency of multi-dimensional index structures. The factors that deteriorate the concurrency of index structures are node splits and minimum bounding region (MBR) updates in multi-dimensional index structures. The proposed concurrency control algorithm introduces PLC(Partial Lock Coupling) technique to avoid lock coupling during MBR updates. Also, a new MBR update method that allows searchers to access nodes where MBR updates are being performed is proposed. To reduce the performance degradation by node splits the proposed algorithm holds exclusive latches not during whole split time but only during physical node split time that occupies the small part of a whole split process. For performance evaluation, we implement the proposed concurrency control algorithm and one of the existing link technique-based algorithms on MIDAS-3 that is a storage system of a BADA-4 DBMS. We show through various experiments that our proposed algorithm outperforms the existing algorithm in terms of throughput and response time. Also, we propose a recovery protocol for our proposed concurrency control algorithm. The recovery protocol is designed to assure high concurrency and fast recovery.