• Journal of information and communication convergence engineering
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• 제9권3호
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.718-720
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• 1999

This paper describes a charge pump PLL architecture which achieves high frequency operation and fast acquisition. This architecture employs multi-phase frequency detector comprised of precharge type phase frequency detector and conventional phase frequency detector. Operation frequency is increased by using precharge type phase frequency detector when the phase difference is small and acquisition time is shortened by using conventional phase frequency detector and increased charge pump current when the phase difference is large. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 694MHz at 3.0V and faster acquisition were achieved by simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.85-88
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• 2000

This paper describes a Band-Selective Charge-Pump PLL(CPPLL) for clock recovery and clock generator. The proposed PLL satisfies fast acquisition time and low jitter characteristics simultaneously by reducing initial frequency error. The acquisition time of the designed Band-Selective CPPLL can be decreased down to 55% of a conventional CPPLL.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권10호
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• ETRI Journal
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• 제32권1호
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• pp.142-144
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• 2010

In this letter, we propose GPS L5 acquisition schemes to detect a fast code phase and improve the accuracy of the Doppler frequency. The proposed approach is based on the code-phase changes which occur during the acquisition processing time originating in the Doppler frequency. The proposed schemes detect a fast code phase within about 1 chip near the estimated code phase and improve the accuracy of the Doppler frequency by up to about 4 times in comparison with the popular Septentrio receiver. The feasibility of the proposed schemes is demonstrated through simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• Journal of Positioning, Navigation, and Timing
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• 제4권4호
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• pp.151-160
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• 2015

GPS L2C signal is a recently added civil signal to L2 frequency and is constructed by time division multiplexing of civil moderate (L2-CM) and civil long (L2-CL) code signals. While the L2-CM code is 20 ms-periodic and modulates satellite navigation message, the L2-CL code is 1.5s-periodic with 767,250 chips long code sequence and carries no data. Therefore, the L2-CL code signal allows receivers to perform a very long coherent integration. However, due to the length of the L2-CL code, the acquisition of the L2-CL code signal may take too long or require too much hardware resources. In this paper, we propose a three-step ultra-fast L2-CL code acquisition (TSCLA) technique for dual band GPS receivers. In the proposed TSCLA technique, a dual band GPS receiver sequentially acquires the coarse/acquisition (C/A) code signal at L1 frequency, the L2-CM code signal, and the L2-CL code signal to minimize mean acquisition time (MAT). The theoretical performance analysis and numerous Monte Carlo simulations show the significant advantage of the proposed TSCLA technique over conventional techniques introduced in the literature.

• 제어로봇시스템학회논문지
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• 제14권6호
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• pp.603-607
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• 2008

This paper proposes a fast acquisition method using INS velocity and multiple correlators for high speed vehicles. In order to reduce acquisition time in GPS receiver, the method utilizes inertial velocity information and multiple correlators. Search range of the Doppler frequency is reduced by using INS velocity and the number of cells at one search can be increased by using multiple correlators. By using both multiple correlators and the INS velocity in the acquisition, search space can be greatly reduced. Experimental results show that the method gives faster signal acquisition performance than the conventional method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.271-274
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• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

• 한국통신학회논문지
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• 제33권6A호
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• pp.685-692
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• 2008

본 논문에서는 Inmarsat (International Marine Satellite) mini-m 시스템의 하향 링크 수신기를 위한 timing recovery 루프를 제안한다. Inmarsat mini-m 시스템 규격에서 요구하는 frequency tolerance는 ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) 이며, timing acquisition 시간은 하나의 UW (Unique Word) 신호 구간인 15ms 이기 때문에 주파수 옵셋에 강인하고 UW 신호 구간에서의 빠른 aquisition 이 가능한 루프 설계가 요구된다. 이에 따라 본 논문에서는 주파수 옵셋에 강인하고 빠른 aquisition 이 가능한 timing recovery 루프를 제안하였으며, 제안된 timing recovery 루프는 UW detector와 UW detector에 의해 검출된 UW 신호를 이용한 timing recovery 루프를 연동한 구조이다. UW detector는 주파수 옵셋 환경에서 안정적인 성능을 위해 차동 기반의 noncoherent detector 방식을 적용하였으며, TED (Timing Error Detector) 알고리즘은 기존의 GAD (Gardner Detector) 알고리즘 대신 본 논문에서 제안하는 UW 신호를 이용한 차동 기반의 ELD (Early Late Detector) 알고리즘 적용하였다. 제안된 방식과 기존의 GAD와의 성능 비교를 통해 제안된 방식이 만족스러운 성능과 신뢰성 있는 동작이 가능함을 입증하였다.