• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.239-242
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• 2008

We study the problem of finding the maximum suffix of a string on the external memory model of computation with one disk. In this model, we are primarily interested in designing algorithms that reduce the number of I/Os between the disk and the internal memory. A string of length N has N suffixes and among these, the lexicographically largest one is called the maximum suffix of the string. Finding the maximum suffix of a string plays a crucial role in solving some string problems. In this paper, we present an external memory algorithm for computing the maximum suffix of a string of length N. The algorithm uses four blocks in the internal memory and performs at most 4(N/L) disk I/Os, where L is the size of a block.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.598-607
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• 2005

We propose a new external-memory index data structure, the Suffix B-tree. The Suffix B-tree is a B-tree in which the key is a string like the String B-tree. While the node in the String B-tree is implemented with a Patricia trio, the node in the Suffix B-tree is implemented with an array. So the Suffix B-tree is simpler and easier to be Implemented than the String B-tree. Nevertheless, the branching algorithm of the Suffix B-tree is as efficient as that of the String B-tree. Consequently, the Suffix B-tree takes the same worst-case disk accesses as the String B-tree to solve the string matching problem, which is fundamental and important in the area of string algorithms.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.72-82
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• 2014

Recently, the size of semiconductor industry market is constantly growing, due to the increase in diffusion of smart-phone, tablet PC and SSD(Solid State Drive). Also, it is expected that the demand for TLC NAND-type flash memory would gradually increase, with the recent release of TLC NAND-type flash memory in the SSD market. There have been a lot of studies on SLC NAND flash memory, but no research on TLC NAND flash memory has been conducted, yet. Also, a test of NAND-type flash memory is depending on a high-priced external equipment. Therefore, this study aims to suggest a structure for an autonomous test with no high-priced external test device by modifying the existing SLC NAND flash memory and MLC NAND flash memory test algorithms and patterns and applying them to TLC NAND flash memory.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2278-2282
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• 2003

In this paper the structure of 2-DOF controller based on artificial immune network algorithms has been suggested for nonlinear system. Up to present time, a number of structures of the 2-DOF controllers are considered as 2-DOF (2-Degrees Of Freedom) control functions. However, a general view is provided that they are the special cases of either the state feedback or the modification of PID controllers. On the other hand, the immune network system possesses a self organizing and distributed memory, also it has an adaptive function by feed back law to its external environment and allows a PDP (parallel distributed processing) network to complete patterns against the environmental situation, since antibody recognizes specific antigens which are the foreign substances that invade living creatures. Therefore, it can provide optimal solution to external environment. Simulation results by immune based 2-DOF controller reveal that immune algorithm is an effective approach to search for 2-DOF controller.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1531-1536
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• 2003

In this paper the structure of 2-DOF controller based on artificial immune network algorithms has been suggested for nonlinear system. Up to present time, a number of structures of the 2-DOF controllers are considered as 2-DOF (2-Degrees Of Freedom) control functions. However, A general view is provided that they are the special cases of either the state feedback or the modification of PID controllers. On the other hand, The immune network system possesses a self organizing and distributed memory, also it has an adaptive function by feed back law to its external environment and allows a PDP (parallel distributed processing) network to complete patterns against the environmental situation, since antibody recognizes specific antigens which are the foreign substances that invade living creatures. Therefore, it can provide optimal solution to external environment. Simulation results by immune based 2-DOF controller reveal that immune algorithm is an effective approach to search for 2-DOF controller.

• Smart Structures and Systems
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• v.15 no.3
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• pp.897-911
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• 2015

This study presents a novel approach based on advancements in Evolutionary Computation for data-driven modeling of complex multi-dimensional memory-dependent systems. The investigated example is a benchmark coupled three-dimensional system that incorporates 6 Bouc-Wen elements, and is subjected to external excitations at three points. The proposed technique of this research adapts Genetic Programming for discovering the optimum structure of the differential equation of an auxiliary variable associated with every specific degree-of-freedom of this system that integrates the imposed effect of vibrations at all other degrees-of-freedom. After the termination of the first phase of the optimization process, a system of differential equations is formed that represent the multi-dimensional hysteretic system. Then, the parameters of this system of differential equations are optimized in the second phase using Genetic Algorithms to yield accurate response estimates globally, because the separately obtained differential equations are coupled essentially, and their true performance can be assessed only when the entire system of coupled differential equations is solved. The resultant model after the second phase of optimization is a low-order low-complexity surrogate computational model that represents the investigated three-dimensional memory-dependent system. Hence, this research presents a promising data-driven modeling technique for obtaining optimized representative models for multi-dimensional hysteretic systems that yield reasonably accurate results, and can be generalized to many problems, in various fields, ranging from engineering to economics as well as biology.