• Title/Summary/Keyword: embedded memory

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A New Embedded Compression Algorithm for Memory Size and Bandwidth Reduction in Wavelet Transform Appliable to JPEG2000 (JPEG2000의 웨이블릿 변환용 메모리 크기 및 대역폭 감소를 위한 새로운 Embedded Compression 알고리즘)

  • Son, Chang-Hoon;Song, Sung-Gun;Kim, Ji-Won;Park, Seong-Mo;Kim, Young-Min
    • Journal of Korea Multimedia Society
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    • v.14 no.1
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    • pp.94-102
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    • 2011
  • To alleviate the size and bandwidth requirement in JPEG2000 system, a new Embedded Compression(EC) algorithm with minor image quality drop is proposed. For both random accessibility and low latency, very simple and efficient hadamard transform based compression algorithm is devised. We reduced LL intermediate memory and code-block memory to about half size and achieved significant memory bandwidth reductions(about 52~73%) through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

Balancing Energy and Memory Consumption for Lifetime Increase of Wireless Sensor Network (무선 센서 네트워크의 수명 연장을 위한 에너지와 메모리의 균형 있는 소모 방법)

  • Kim, Tae-Rim
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.6
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    • pp.361-367
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    • 2014
  • This paper introduces balancing energy and memory consumption for lifetime increase of wireless sensor network. In cluster-based wireless sensor network, sensor nodes adjacent of cluster heads have a tendency to deplete their own battery energy and cluster heads occupy memory space significantly. If the nodes close to region where events occur frequently consume their energy and memory fully, network might be destroyed even though most of nodes are still alive. Therefore, it needs to balance network energy and memory with consideration of event occurrence probability so that network lifetime is increased. We show a method of balancing wireless sensor network energy and memory to organize cluster groups and elect cluster heads in terms of event occurrence probability.

A File System for Large-scale NAND Flash Memory Based Storage System

  • Son, Sunghoon
    • Journal of the Korea Society of Computer and Information
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    • v.22 no.9
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    • pp.1-8
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    • 2017
  • In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

Programmable Memory BIST for Embedded Memory (내장 메모리를 위한 프로그램 가능한 자체 테스트)

  • Hong, Won-Gi;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.61-70
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    • 2007
  • The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

Quad-functional Built-in Test Circuit for DRAM-frame-memory Embedded SOG-LCD

  • Takatori, Kenichi;Haga, Hiroshi;Nonaka, Yoshihiro;Asada, Hideki
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.914-917
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    • 2008
  • A quad-functional built-in test circuit has been developed for DRAM-frame-memory embedded SOG-LCDs. The quad function consists of memory test, display test, serial transfer test, and parallel transfer test which is the normal operation mode for our SOG-LCD. Results of memory and display tests are shown.

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Efficient Utilization of Burst Data Transfers of DMA (직접 메모리 접근 장치에서 버스트 데이터 전송 기능의 효과적인 활용)

  • Lee, Jongwon;Cho, Doosan;Paek, Yunheung
    • IEMEK Journal of Embedded Systems and Applications
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    • v.8 no.5
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    • pp.255-264
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    • 2013
  • Resolving of memory access latency is one of the most important problems in modern embedded system design. Recently, tons of studies are presented to reduce and hide the access latency. Burst/page data transfer modes are representative hardware techniques for achieving such purpose. The burst data transfer capability offers an average access time reduction of more than 65 percent for an eight-word sequential transfer. However, solution of utilizing such burst data transfer to improve memory performance has not been accomplished at commercial level. Therefore, this paper presents a new technique that provides the maximum utilization of burst transfer for memory accesses with local variables in code by reorganizing variables placement.

Implementation of A Low-Power Embedded System via Scratch-pad Memory Compression (스크래치 패드 메모리의 압축을 통한 저전력 임베디드 시스템의 구현)

  • Suh, Hyo-Joong
    • The KIPS Transactions:PartA
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    • v.15A no.5
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    • pp.269-274
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    • 2008
  • Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.

A Study on the Performance Factors of File System in General Purposed Embedded Systems (범용 임베디드 시스템에서 파일 시스템의 성능 인자 연구)

  • Choi, Jin-oh;Kim, Soo-hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.187-189
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    • 2012
  • The embedded systems commonly equip a file system as default to keep data. This file system is mostly constructed with flash memory as the price get lower and the performance get higher. Types of the file system implemented on the flash memory are various according to types of embedded operating systems. By the way, as the embedded systems increasingly depend on the file system, a selection of the file system type of the embedded systems influences the performance of the entire system. This thesis discusses the factors to influence the performance of entire system in construction of file system and selection of the types, and discusses the research results.

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Way-set Associative Management for Low Power Hybrid L2 Cache Memory (고성능 저전력 하이브리드 L2 캐시 메모리를 위한 연관사상 집합 관리)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.3
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    • pp.125-131
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    • 2018
  • STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

An Implementation of Single Stack Multi-threading for Small Embedded Systems

  • Kim, Yong-Seok
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.4
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    • pp.1-8
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    • 2016
  • In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.