1 |
M. Ekman, P. Stenstrom, "A Robust Main-memory Compression Scheme," Int'l Symp. Computer Architecture, pp.74-85, 2005
|
2 |
M. Kjelso, M. Gooch, S. Jones. "Performance Evaluation of Computer Architectures with Main Memory Data Compression", Journal of Systems Architecture. Vol.45, pp.571-590, 1999
DOI
ScienceOn
|
3 |
P. Wilson, S. Kaplan, Y. Smaragdakis, "The Case for Compressed Caching in Virtual Memory Systems", USENIX Ann. Technical Conf., pp.101-116, 1999
|
4 |
R. S. De Castro, A. P. Do Lago, D. da Silva, "Adaptive Compressed Caching: Design and Implementation" Symp. Computer Architecture and High-Performance Computing, pp.10-18, 2003
|
5 |
B. Abali, H. Franke, X. Shen, D. Poff, B. Smith, "Performance of Hardware Compressed Main Memory", Int'l Symp. High-Performance Computer Architecture, pp.73-81, 2001
|
6 |
L. Wang, W. Tembe, S. Pande, "Optimizing On-chip Memory Usage Through Loop Restructuring for Embedded Processors", Int.l Conf. Compiler Construction, pp.141-156, 2000
|
7 |
O. Ozturk, M. Kandemir, I. Demirkiran, G. Chen, M.J. Irwin, "Data Compression for Improving SPM Behavior", Design Automation Conf. pp.401-406, 2004
|
8 |
GDM1202 Developer's Manual, GCT Semiconductor
|
9 |
T. A. Welch, "A Technique for High Performance Data Compression," IEEE Computer, Vol.17, No.6, pages 8-19, 1984
|
10 |
Bluetooth Specification 1.2, Bluetooth SIG. Inc
|
11 |
W. Wolf, Computers as Components: Principles of Embedded Computing System Design, Morgan Kaufmann Publishers Inc., 2001
|
12 |
Y. Yang, R. Gupta, "Frequent-Value Locality and its Applications", ACM Trans. on Embedded Computing Systems, Vol.1, pp.79-105, 2002
DOI
|
13 |
M. Farrens, A. Park, "Dynamic Base Register Caching: A technique for Reducing Address Bus Width", Int'l Symp. Computer Architecture, 1991
|
14 |
F. Douglis, "The Compression Cache: Using On-line Compression to Extend Physical memory" USENIX Conf., pp.519-529, 1993
|
15 |
J.-S. Lee, W.-K. Hong, S.-D. Kim, "Design and Evaluation of a Selective Compressed Memory System," Int'l Conf. Computer Design, pp.184-191, 1999
DOI
|
16 |
M. Kandemir, J. Ramanujam, M.J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh, "Dynamic Management of Scratch-pad Memory Space", Design Automation Conf., pp.690-695, 2001
|
17 |
R.B. Tremaine, P.A. Franaszek, J.T. Robinson, C.O. Schulz, T. B. Smith, M. E. Wazlowski, P.M. Bland, "IBM Memory Expansion Technology (MXT)", IBM Journal Research & Development, Vol.45 No.2, pp.271-285, 2001
DOI
|
18 |
A.R. Alameldeen, D.A. Wood, "Frequent Pattern Compression: a Significance-based Compression Scheme for L2 Caches", Technical Report 1500, Computer Sciences Dept,, Univ, Wisconsin-Madison, 2004
|
19 |
P. R. Panda, N. D. Dutt, A. Nicolau, "Efficient Utilization of Scratch-pad Memory in Embedded Processor Applications", European Design and Test Conf., 1997
|
20 |
Y. Zhang, J. Yang, and R. Gupta, "Frequent Value Locality and Value-centric Data Cache design", Int'l Conf' Architectural Support for Programming Languages and Operating Systems, pp.150-159, 2000
DOI
|
21 |
M. Balakrishnan, P. Marwedel, L. Wehmeyer, N. Grunwald, R. Banakar, S. Steinke, "Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory", Int'l Symp. System Synthesis, pp.213-218, 2002
DOI
|
22 |
G. Keramidas, K. Aisopos, S. Kaxiras, "Dynamic Dictionary-Based Data Compression for Level-1 Caches", Lecture Notes in Computer Science, Vol3894/2006, pp.114-129, 2006
DOI
ScienceOn
|
23 |
M. Kjelso, M. Gooch, S. Jones, "Design and Performance of a Main Memory Hardware Data Compressor", EUROMICRO Conf., pp.423-430, 1996
|