1 |
ARM, "CoreLink DMA Controllers," Technical reference manual, 2009.
|
2 |
J. Mangino, "Using DMA with high performance peripherals to maximize system performance," Texas Instrument report, 2007.
|
3 |
Samsung, "Exynos 4 quad," technical document, 2012.
|
4 |
J. Barth, J. Dreibelbis, E. Nelson, "Embedded DRAM design and architecture for the IBM 0.11um ASIC offering," IBM Journal of Research and Development, Vol. 46, No. 6, pp.675-680, 2002.
DOI
|
5 |
Fujitsu, "FR80S/T series DMA access speed," hardware manual AN07-00156-1E, 2008.
|
6 |
STMicroelectronics, "STM DMA API," technical manual, 2011.
|
7 |
D. Bartely, "Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes," Software Practice & Experience Vol. 22, No. 2, pp.101-110, 1992.
DOI
|
8 |
S. Liao, S. Devadas, K. Keutzer, S. Tjiang, "Storage Assignment to Decrease Code Size," Proceedings on SIGPLAN Conference of PLDI, pp.186-195, 1995.
|
9 |
S. Liao, S. Devadas, K. Keutzer, S. Tjiang, A. Wang, "Storage Assignment to Decrease Code Size," ACM TOPLAS, Vol. 18, No. 3, pp.235-253, 1996.
DOI
ScienceOn
|
10 |
V.K. Nandivada, J. Palsberg, "SARA: combining stack allocation and register allocation," Proceedings on International Conference on Compiler Construction, pp.232-246, 2006.
|
11 |
ARM, "ARM architecture reference manual," 2007.
|
12 |
P. Shivakumar, N.P. Jouppi, "CACTI 3.0: an integrated cache timing, power and area model," HP Labs, Palo Alto, CA, Technical Report, 2001.
|
13 |
V. Zivojnovic, J.M. Velarde, C. Schager, H. Meyr, "DSPStone- A DSP oriented Benchmarking Methodology," Proceedings on International Conference of Signal Processing Applications and Technology, 1994.
|
14 |
C. Lee, M. Potkonjak, W Mangione-Smith. "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," Proceedings on IEEE International Symposium of Microarchitecture, pp.330-335, 1997.
|