• Title/Summary/Keyword: electroplating package

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The Effect of SiC Nanopaticles on Interface of Micro-bump manufactured by electroplating (나노입자가 전해도금으로 형성된 미세범프의 계면에 미치는 영향)

  • Sin, Ui-Seon;Lee, Se-Hyeong;Lee, Chang-U;Jeong, Seung-Bu;Kim, Jeong-Han
    • Proceedings of the KWS Conference
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    • 2007.11a
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    • pp.245-247
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    • 2007
  • Sn-base solder bump is mainly used in micro-joining for flip chip package. The quantity of intermetallic compounds that was formed between Cu pad and solder interface importantly affects reliability. In this research, micro-bump was fabricated by two binary electroplating and the intermetallic compounds(IMCs) was estimated quantitatively. When the micro Sn-Ag solder bump was made by electroplating, SiC powder was added in the plating solution for protecting of intermetallic growth. Then, the intermetallic compounds growth was decrease with increase of amount of SiC power. However, if the mount of SiC particle exceeds 4 g/L, the effect of the growth restraint decrease rapidly.

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Precise composition control of Sn-3.0Ag-0.5Cu lead free solder bumping made by two binary electroplating (이원계 전해도금법에 의한 Sn-3.0Ag-0.5Cu 무연솔더 범핑의 정밀 조성제어)

  • Lee Se-Hyeong;Lee Chang-U;Gang Nam-Hyeon;Kim Jun-Gi;Kim Jeong-Han
    • Proceedings of the KWS Conference
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    • 2006.05a
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    • pp.218-220
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    • 2006
  • Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

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The Effects of Current Types on Through Via Hole Filling for 3D-SiP Application (전류인가 방법이 3D-SiP용 Through Via Hole의 Filling에 미치는 영향)

  • Chang, Gun-Ho;Lee, Jae-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.4
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    • pp.45-50
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    • 2006
  • Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

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Cu Via-Filling Characteristics with Rotating-Speed Variation of the Rotating Disc Electrode for Chip-stack-package Applications (칩 스택 패키지에 적용을 위한 Rotating Disc Electrode의 회전속도에 따른 Cu Via Filling 특성 분석)

  • Lee, Kwang-Yong;Oh, Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.14 no.3
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    • pp.65-71
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    • 2007
  • For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

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Electroplating of Copper Using Pulse-Reverse Electroplating Method for SiP Via Filling (펄스-역펄스 전착법을 이용한 SiP용 via의 구리 충진에 관한 연구)

  • Bae J. S.;Chang G H.;Lee J. H.
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.2 s.35
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    • pp.129-134
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    • 2005
  • Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

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A Study on Wafer-Level Package of RF MEMS Devices Using Dry Film Resist (Dry Film Resist를 이용한 RF MEMS 소자의 기판단위 실장에 대한 연구)

  • Kang, Sung-Chan;Kim, Hyeon-Cheol;Chun, Kuk-Jin
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.379-380
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    • 2008
  • This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

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Wafer Level Packaging of RF-MEMS Devices with Vertical feed-through (Ultra Thin 실리콘 웨이퍼를 이용한 RF-MEMS 소자의 웨이퍼 레벨 패키징)

  • 김용국;박윤권;김재경;주병권
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.12S
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    • pp.1237-1241
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    • 2003
  • In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

Characteristics of Sn-Pb Electroplating and Bump Formation for Flip Chip Fabrication (전해도금에 의해 제조된 플립칩 솔더 범프의 특성)

  • Hwang, Hyeon;Hong, Soon-Min;Kang, Choon-Sik;Jung, Jae-Pil
    • Journal of Welding and Joining
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    • v.19 no.5
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    • pp.520-525
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    • 2001
  • The Sn-Pb eutectic solder bump formation ($150\mu\textrm{m}$ diameter, $250\mu\textrm{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Pb deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased wish increasing time. The plating rate became constant at limiting current density. After the characteristics of Sn-Pb plating were investigated, Sn-Pb solder bumps were fabricated in optimal condition of $7A/dm^$. 4hr. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallurgy). The shear strength of Sn-Pb bump after reflow was higher than that of before reflow.

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Fabrication of Through-hole Interconnect in Si Wafer for 3D Package (3D 패키지용 관통 전극 형성에 관한 연구)

  • Kim, Dae-Gon;Kim, Jong-Woong;Ha, Sang-Su;Jung, Jae-Pil;Shin, Young-Eui;Moon, Jeong-Hoon;Jung, Seung-Boo
    • Journal of Welding and Joining
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    • v.24 no.2
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    • pp.64-70
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    • 2006
  • The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.