• 대한용접접합학회:학술대회논문집
• /
• 대한용접접합학회 2007년 추계학술발표대회 개요집
• /
• pp.245-247
• /
• 2007

Sn-base solder bump is mainly used in micro-joining for flip chip package. The quantity of intermetallic compounds that was formed between Cu pad and solder interface importantly affects reliability. In this research, micro-bump was fabricated by two binary electroplating and the intermetallic compounds(IMCs) was estimated quantitatively. When the micro Sn-Ag solder bump was made by electroplating, SiC powder was added in the plating solution for protecting of intermetallic growth. Then, the intermetallic compounds growth was decrease with increase of amount of SiC power. However, if the mount of SiC particle exceeds 4 g/L, the effect of the growth restraint decrease rapidly.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 1998년도 추계학술발표강연 및 논문개요집
• /
• pp.80-80
• /
• 1998

• 대한용접접합학회:학술대회논문집
• /
• 대한용접접합학회 2006년도 춘계 학술대회 개요집
• /
• pp.218-220
• /
• 2006

Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

• 마이크로전자및패키징학회지
• /
• 제13권4호
• /
• pp.45-50
• /
• 2006

3D package의 SiP에서 구리의 via filling은 매우 중요한 사항으로 package밀도가 높아짐에 따라 via의 크기가 줄어들며 전기도금법을 이용한 via filling이 연구되어왔다. Via filling시 via 내부에 결함이 발생하기 쉬운데 전해액 내에 억제제, 가속제등 첨가제를 첨가하고 펄스-역펄스(PRC)의 전류파형을 인가하여 결함이 없는 via의 filling이 가능하다. 본 연구에서는 건식 식각 방법 중 하나인 DRIE법을 이용하여 깊이 $100{\sim}190\;{\mu}m$, 직경이 각각 $50{\mu}m,\;20{\mu}m$인 2가지 형태의 via을 형성하였다. DRIE로 via가 형성된 Si wafer위에 IMP System으로 Cu의 Si으로 확산을 막기 위한 Ta층과 전해도금의 씨앗층인 Cu층을 형성하였다. Via시편은 직류, 펄스-역펄스의 전류 파형과 억제제, 가속제, 억제제의 첨가제를 모두 사용하여 filling을 시도하였고, 공정 후 via의 단면을 경면 가공하여 SEM으로 관찰하였다.

• 마이크로전자및패키징학회지
• /
• 제14권3호
• /
• pp.65-71
• /
• 2007

칩 스택 패키지에 적용을 위해 폭 $75{\sim}10\;{\mu}m$, 길이 3mm의 트랜치 비아에 대해 도금전류밀도 및 rotating disc electrode(RDE)의 회전속도에 따른 Cu filling 특성을 분석하였다. RDE 속도가 증가함에 따라 트랜치 비아의 Cu filling 특성이 향상되었다. 트랜치 비아의 반폭 길이, 즉 트랜치 비아 폭의 1/2 길이와 이 트랜치 비아에 대해 95% 이상의 Cu filling 비를 얻기 위한 RDE 최소속도 사이에는 Nernst 관계식이 성립하여, 95%이상의 Cu filling비를 얻을 수 있는 최소 트랜치 비아의 반폭 길이는 RDE 속도의 제곱근의 역수에 직선적으로 비례하였다.

• 마이크로전자및패키징학회지
• /
• 제12권2호
• /
• pp.129-134
• /
• 2005

SiP의 3D패키지에 있어서 구리도금은 매우 중요한 역할을 한다 이러한 구리 도금의 조건을 알아보기 위하여 조건이 다른 전해질에서 전기화학적 I-V특성을 분석하였다. 첨가제로 억제제와 촉진제의 특성을 분석하였다. 3D 패키지에 있어서 직경 50, 75, $100{\mu}m$의 via를 사용하였다. Via의 높이는 $100{\mu}m$로 동일하였다. Via의 내부는 확산방지층으로 Ta을 전도성 씨앗층으로 Cu를 magnetron 스퍼터링 방법으로 도포하였다. 직류, 펄스, 펄스-역펄스 등 전류의 파형을 변화시키면서 구리 도금을 하였다. 직류만 사용하였을 경우에는 결함 없이 via가 채워지지 않았으며 펄스도금을 한 경우 구리 충진이 개선을 되었으나 결함이 발생하였다. 펄스-역펄스를 사용한 경우 결함 없는 구리 충진층을 얻을 수 있었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.379-380
• /
• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

• 한국전기전자재료학회논문지
• /
• 제16권12S호
• /
• pp.1237-1241
• /
• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Journal of Welding and Joining
• /
• 제19권5호
• /
• pp.520-525
• /
• 2001

The Sn-Pb eutectic solder bump formation ($150\mu\textrm{m}$ diameter, $250\mu\textrm{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Pb deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased wish increasing time. The plating rate became constant at limiting current density. After the characteristics of Sn-Pb plating were investigated, Sn-Pb solder bumps were fabricated in optimal condition of $7A/dm^$. 4hr. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallurgy). The shear strength of Sn-Pb bump after reflow was higher than that of before reflow.

• Journal of Welding and Joining
• /
• 제24권2호
• /
• pp.64-70
• /
• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.