• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.350-350
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• 2010

Silicon carbide (SiC), one of the well known wide band gap semiconductors, shows high thermal conductivities, chemical inertness and breakdown energies. The design of normally-off 4H-SiC VJFETs [1] has been reported and 4H-SiC VJFETs with different lateral JFET channel opening dimensions have been studied [2]. In this work, 4H-SiC based VJFETs has been designed using the device simulator (ATLAS, Silvaco Data System, Inc). We varied the n-epi layer thickness (from $6\;{\mu}m$ to $10\;{\mu}m$) and the channel width (from $0.9\;{\mu}m$ to $1.2\;{\mu}m$), and investigated the static characteristics as blocking voltages, threshold voltages, on-resistances. We have shown that silicon carbide JFET structures of highly intensified blocking voltages with optimized figures of merit can thus be achieved by adjusting the epi layer thickness and channel width.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.813-817
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• 2006

In this paper, we analyzed the breakdown voltage and on-resistance of the multi-RESURF SOI LDMOSFET as a function of epi-layer concentration. P-/n-epi layer thickness and doping concentration of the proposed structure are varied from $2{\sim}5{\mu}m\;and\;1\{times}10^{15}/cm^{3}^{\sim}9\{times}10^{15}/cm^{3}$ to find optimum breakdown voltage and on-resistance of the proposed structure. The maximum breakdown voltage of the proposed structure is $224\;V\;at\;R_{on}=0.2{\Omega}-mon^{2}\;with\;P_{epi}=3\{times}10^{15}/cm^{3},\;N_{epi}=7\{times}10^{15}/cm^{3}\;and\;L_{epi}=10{\mu}m$. Characteristics of the device are verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.145-145
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• 2008

갈륨-질화물(GaN) 기반의 고속전자이동도 트랜지스터(high electron mobility transistor, HEMT)는 최근 마이크로파 또는 밀리미터파 등의 차세대 고주파용 전력소자로 각광받고 있다. AlGaN/GaN HEMT는 이종접합구조(heterostructure) 로부터 발생하는 이차원 전자가스(two-dimensional electron gas, 2DEG) 채널을 이용하여 높은 전자 이동도, 높은 항복전압 및 우수한 고출력 특성을 얻는 것이 가능하다. AlGaN/GaN HEMT에서 ohmic 전극 부분과 채널이 형성되는 부분과의 거리에 의한 저항의 성분을 줄이고 전자의 터널링의 확률을 증가시키기 위해서 recess된 구조가 많이 사용되고 있다. 그러나 이 구조에서는 recess된 소스와 드레인에 의해 AlGaN층의 제거로 AlGaN층의 두께에 영향을 미치며 그에 따라 채널에 생성되는 전자의 농도를 변화시키게 된다. 본 논문에서는 소스와 드레인의 Trench 구조를 제안하였다. ohmic 전극 부분과 채널간의 거리의 감소로 특성을 향상시켜서 recess 구조의 장점이 유지된다. 그리고 recess되는 소스와 드레인 영역에서 AlGaN층을 전체적으로 제거하는 것이 아니고 Trench 즉 일부분만 제거하면서 AlGaN층의 두께의 변화에 따른 문제점도 줄일 수 있다. 따라서 이러한 전극 부분을 Trench구조화 시킨 AlGaN/GaN HEMT의 DC특성을 $ATLAS^{TM}$를 이용하여 전산모사하고 최적화된 구조를 제안하였다.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• Journal of IKEEE
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• v.24 no.4
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• pp.1167-1171
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• 2020

In this work, we proposed a graded gate-doping structure to alleviate an electric field in p-GaN gate layer in order to improve the reliability of normally-off GaN power devices. In a TCAD simulation by Silvaco Atlas, a distribution of the graded p-type doping concentration was optimized to have a threshold voltage and an output current characteristics as same as the reference device with a uniform p-type gate doping. The reduction of an maximum electric field in p-GaN gate layer was observed and it suggests that the gate reliability of p-GaN gate HFETs can be improved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.1-7
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• 2006

This is a preliminary study on the MEMS(Miro Electro Mechanical System) electrostatic power generator. It suggested a converting device to change from the electrostatic to the dynamic electricity. To testify, it used Silvaco simulation tools(Athena and Atlas) and fabricated the converting device. The result of the simulation and test it seems to convert electrostatic into dynamic electricity effectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.445-447
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• 2014

최근에 전자문화지도에 대한 관심이 늘어나면서 다양한 주제를 기반으로 한 전자문화지도들이 연구 및 개발되고 있는 추세이다. 그러나 기존의 전자문화지도들은 대부분 단일 주제로 제작되므로 주제들 간의 연관성 분석이 어렵고, 전자문화지도들이 서로 연계되어 있지 않아 다양한 관점을 기반으로 한 활용이 미흡한 문제점이 있다. 본 논문에서는 이러한 문제점을 해결하기 위하여 하나의 전자문화지도에 레이어 기능을 활용하여 다양한 주제들을 표현하는 방안을 제시한다. 또한, 이를 기반으로 전자문화지도에서의 주제별 중첩 기능을 활용하여 주제들 간의 연계 관계를 효율적으로 파악하고 다양한 주제들의 연관 관계를 통해 새로운 지식을 도출해 낼 수 있는 활용 방안을 제시하고자 한다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.229-232
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• 2001

4H-SIC(silicon carbide) MESFET large signal model was studied using modified Materka-Kacprzak large signal MESFET model. 4H-SiC MESFET device simulation have been conducted by Silvaco's 2D device simulator, ATLAS. The result is modeled using modified Materka large signal model. simulation and modeling results are -8V pinch off voltage, under $V_{GS=0V}$, $V_{DS=25V}$ conditions, $I_{DSS=270㎃}$mm, $G_{m=45㎳}$mm were obtained. Through the power simulation 2GHz, at the bias of $V_{GS=-4V}$ and $V_{DS=25V}$, 10dB Gain, 34dBm(1dB compression point)output power, 7.6W/mm power density, 37% PAE(power added efficiency) were obtained.d.d.d.