• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1972-1975
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• 2002

In this paper, we have proposed low temperature co-fired ceramic (LTCC) based packaging for RF MEMS devices. The packaging structure is designed and evaluated with 3D full field simulation. 50 ${\Omega}$ matched coplanar waveguide(CPW) transmission line is employed as the test vehicle to evaluate the performances of the proposed package structure. The line is encapsulated with the LTCC packaging lid and connected to the via feed line. To reduce the insertion loss due to the packaging lid, the cavity with via post is formed in the packaging lid. The performances of the package structure is simulated with the different cavity depth and via-to-via length. Simulation results show that the proposed package structure has reflection loss better than 20 dB and insertion loss lower than 0.1 dB from DC to 30 GHz with the cavity depth and via-to-via length of 300 ${\mu}m$ and 350 ${\mu}m$, respectively. To realize the designed package structure, the cavity patterning is tested using the sandblast of LTCC.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권4호
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• pp.441-446
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• 2013

A thermal model of power modules based on the physical dimension and thermal properties is proposed in this paper. The heat path in the power module is considered as a one-dimensional heat transfer in the model. The method of the parameters extraction for the model is given in the paper. With high speed and accuracy, the thermal model is suit for electrothermal simulation. The proposed model is verified by experimental results.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.99.1-99.1
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• 2016

The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

• 한국전기전자재료학회논문지
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• 제33권5호
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• pp.350-354
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• 2020

In this study, a pressure sensor for each displacement was fabricated based on the silicon-based pressure sensor obtained through simulation results. Wires were bonded to the pressure sensor, and a piezoresistive pressure sensor was inserted into the printed circuit board (PCB) base by directly connecting a micro-electro-mechanical system (MEMS) sensor and a readout integrated circuit (ROIC) for signal processing. In addition, to prevent exposure, a non-conductive liquid silicone was injected into the sensor and the entire ROIC using a pipette. The packaging proceeded to block from the outside. Performing such packaging, comparing simple contact with strong contact, and confirming that the measured pulse wavelength appears accurately.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권1호
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• pp.37-40
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• 2001

New package process for PDP was proposed based on the glass-to-glass vacuum-electrostatic bonding process and tubeless packaging concept derived from the previous study. Hermeticity and operating performance of PDP test panel through the seal-off process application and the possibility for practical use might be high if the process simplicity and productivity-related effort was sequentially carried out.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권4호
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• pp.275-280
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• 1999

The glass-to-glass electrostatic bonding process in vacuum environment was developed and the tubeless-packaged FED was fabricated based on the bonding process. The fabricated tubeless-packaged FED showed stable field emission characteristics and potential applicability to the FED tubeless packaging and vacuum in-line sealing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.33-33
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• 2007

SoP-L 공정은 유전율이 상이한 재료를 이용하여 PCB 공정이 가능하고 다른 packaging 방법에 비해 공정 시간과 비용이 절약되는 잠정이 있다. 본 연구에서는 SoP-L 기술을 이용하여 Si 기판의 함몰에 판한 공정의 안정도와 함몰 시 제작된 때턴의 특성의 변화에 대해 관찰 하였다. Si 기판의 함몰에 Active device를 이용하여 특성의 변화를 살펴보고 공정의 안정도를 확립하려 했지만 Active device는 측정 시 bias의 확보와 특성의 민감한 변화로 인해 비교적 측정이 용이하고 공정의 test 지표를 삼기 위해 passive device 를 구현하여 함몰해 보았다. Passive device 의 제작 과정은 Si 기판 위에 spin coating을 통해 PI(Poly Imide)를 10um로 적층한 후에 Cr과 Au를 seed layer로 증착을 하였다. 그리고 photo lithography 공정을 통하여 photo resister patterning 후에 전해 Cu 도금을 거쳐 CPW 구조로 $50{\Omega}$ line 과 inductor를 형성하였다. 제작 된 passive device의 함몰 전 특성 추출 data와 SoP-L공정을 통한 함몰 후 추출 data 비교를 통해 특성의 변화와 공정의 안정도를 확립하였다. 차후 안정된 SoP-L 공정을 이용하여 Active device를 함몰 한다면 특성의 변화 없이 size 룰 줄이는 효과와 외부 자극에 신뢰도가 강한 기판이 제작 될 것으로 예상된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.315-315
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• 2010

휴대용 전자 기기는 얇고 가벼우면서 빠른 대용량을 처리하는 속도와 다기능이 필요한 추세로 가고 있다. 기기 크기가 작아짐에 따라서 내장 되는 칩 또한 소형화, 고집적화, 고성능화가 요구되므로 이에 상응하는 발전된 패키징 기술이 필요하게 되었고, 이에 대응하기위해서 embedded components device 패키징 기술이 필요로 하게 되었다. 본 연구에서는 $21{\Omega}$ 의 저항 값을 갖는 1005 수동 소자를 prepreg를 이용하여 PCB기판에 내장 한 후 micro via를 이용하여 무전해 구리 도금으로 전기적인 연결을 하여 기판을 제작하였다. 제작되어진 기판으로 Reflow, Aging 테스트 후 칩과 계면간의 금속화합물 반응을 관찰하였다. 또한 Reflow외 시효처리를 끝마친 기판을 사용하여 drop test를 실시한 후 fail 발생 시 저항 값의 변화와 접합부의 미세조직을 관찰하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.317-317
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• 2010

전자기기의 수요 증가와 함께 기기의 소형화, 고집적화가 요구되어짐에 따라 packaging 기술 개발에서 필요한 소재에 관한 연구가 활발히 진행되고 있다. 이에 따라 우수한 절연특성, 낮은 열팽창계수와 낮은 흡습도를 갖고 있으며 무엇보다도 플렉시블하여 3차원 조립이 가능한 LCP가 차세대 기판 부품소재로 많이 거론되고 있다. 그러나 LCP는 구리 동박을 열 압착하여 패턴을 형성하므로 미세 패턴제작이 어려운 문제점이 있다. 본 연구에서는 LCP의 열가소성 특성을 이용하여 seed 구리 도금 층을 형성하여 열 압착 후 패턴 도금 법으로 $10{\mu}m$ 이하의 패턴을 형성하였으며 구리층과 LCP 간의 접합강도를 열 압착 온도 별로 측정하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)