• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.71-74
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• 2003

In this paper, electrical properties of photovoltaic module have been observed for 5 years and found to drop around 5 to 25 %. Element technologies which are critical to electrical loss were therefore examined and dark I-V curve were observed with different soldering conditions. From the results, series resistance decreased with the decrease of contact resistance regardless of temperature conditions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Transactions on Electrical and Electronic Materials
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• 제13권2호
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• pp.78-84
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• 2012

An in-situ optical monitoring method for real-time process monitoring of electrochemical copper deposition (CED) is presented. Process variables to be controlled in achieving desired process results are numerous in the CED process, and the importance of the chemical bath conditions cannot be overemphasized for a successful process. Conventional monitoring of the chemical solution for CED relies on the pH value of the solution, electrical voltage level for the reduction of metal cations, and gravity measurement by immersing sensors into a plating bath. We propose a nonintrusive optical monitoring technique using three types of optical sensors such as chromatic sensors and UV/VIS spectroscopy sensors as potential candidates as a feasible optical monitoring method. By monitoring the color of the plating solution in the bath, we revealed that optically acquired information is strongly related to the thickness of the deposited copper on the wafers, and that the chromatic information is inversely proportional to the ratio of $Cu$ (111) and {$Cu$ (111)+$Cu$ (200)}, which can used to measure the quality of the chemical solution for electrochemical copper deposition in advanced interconnection technology.

• 한국재료학회지
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• 제24권4호
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• ETRI Journal
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• 제35권6호
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• 마이크로전자및패키징학회지
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• 제6권4호
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• pp.61-71
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• 1999

통신분야에서 사용주파수대역의 증가, 제품의 소형화 및 가격경쟁력등의 요구에 따라 RF 소자의 패키징 기술도 플라스틱 패키지 대신에 flip chip interconnection, MCM(multichip module)등과 같은 고밀도 실장기술이 발전해가고 있다. 따라서, 본 논문은 최근 수년간 보고된 응용사례를 중심으로 RF flip chip의 기술적인 개발방향과 장점들을 분석하였고, RF 소자 및 시스템의 개발단계에 따른 적합한 적용기술을 제시하였다. RF flip chip의 기술동향을 요약하면, 1) RF chip배선은 microstrip 대신에 CPW 구조을 선택하며, 2) wafer back-side grinding을 하지 않아서 제조공정이 단순하고 wafer 파손이 적어 제조비용을 낮출 수 있고, 3) wire bonding 패키징에 비해 전기적인 특성이 우수하고 고집적의 송수신 모듈개발에 적합하다는 것이다. 그러나, CPW 배선구조의 RF flip chip 특성에 대한 충분한 연구가 필요하며 RF flip chip의 초기 개발 단계에서 flip chip interconnection 방법으로는 Au stud bump bonding이 적합할 것으로 제안한다.

• 마이크로전자및패키징학회지
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• 제6권2호
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.869-872
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• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 C
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• pp.519-521
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• 2000

The application of low dieletric constant material instead of $SiO_2$ has been considered to reduce interconnection delay, crosstalk, power exhaustion. Methylsilsesquioxane (MSSQ) have a dieletric constant less than k>3 which is lower than that for the convention $SiO_2$ insulator ($k{\sim}4$). The Propose of this study is to know etching rate of MSSQ. Expermentation in this paper use RIE(Reactive ion Etching) and centre) flow rate of $CF_4/O_2$ gas, RF power.

• 한국산학기술학회논문지
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• 제14권4호
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• pp.1935-1941
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• 2013

IP 주소 공간의 부족 문제를 해결하기 위해 NAT(Network Address Translation) 기술을 활용할 수 있다. NAT의 주소 변환 테이블에 없는 바인딩과 관련된 패킷을 제거하는 필터링 특성 때문에 NAT Traversal 문제가 발생한다. 이러한 문제를 해결하기 위해 부가적인 장비를 활용한 여러 가지 방법들이 제시되었다. 최근의 네트워크 시장은 유선과 무선이 통합되는 형태로 발전하고 있으며, 이를 효과적으로 제어하기 위하여 IMS(IP Multimedia Subsystem)라는 유무선 통합 제어 망이 등장하였다. IMS에서 IBCF(Interconnection Border Control Function)와 IBGF(Interconnection Border Gateway Function)라는 부가적인 장비를 이용하여 NAT Traversal 문제를 해결하고 있다. 본 논문에서는 P-CSCF(Proxy-Call Session Control Function)를 활용하여 부가적인 장비를 사용하지 않고 NAT Traversal 문제를 해결하는 방안을 제안한다.