Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2006.06a
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- Pages.595-596
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- 2006
Stacked packaging using vertical interconnection based on Si-through via
Si-관통 전극에 의한 수직 접속을 이용한 적층 실장
- Jeong, Jin-Woo (School of Electrical Engineering and Computer Science, Seoul National University) ;
- Lee, Eun-Sung (School of Electrical Engineering and Computer Science, Seoul National University) ;
- Kim, Hyeon-Cheol (School of Electrical Engineering and Computer Science, Seoul National University) ;
- Moon, Chang-Youl (Samsung Advanced Institute of Technology (SAIT)) ;
- Chun, Kuk-Jin (School of Electrical Engineering and Computer Science, Seoul National University)
- 정진우 (서울대학교 전기 컴퓨터 공학부) ;
- 이은성 (서울대학교 전기 컴퓨터 공학부) ;
- 김현철 (서울대학교 전기 컴퓨터 공학부) ;
- 문창렬 (삼성 종합 기술원 Packaging Center) ;
- 전국진 (서울대학교 전기 컴퓨터 공학부)
- Published : 2006.06.21
Abstract
A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of
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