• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.107-116
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• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.261-263
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• 2002

CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.571-574
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• 2009

Metal oxide/metal bilayer structures are explored as contacts with a low injection barrier in organic thin-film transistors (OTFTs) in an effort to realize their true potential for low-cost electronics. OTFTs with a bilayer electrode of $WO_3$ (10nm) and Al shows a saturation mobility as large as 0.97 $cm^2$/Vsec which are comparable to those of Au-based control samples (~0.90 $cm^2$/Vsec). Scaling of contact resistance with respect to the thickness of $WO_3$ layer is also discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1118-1121
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• 2009

We have fabricated inverted staggered pentacene Thin Film Transistor (TFT) with 1-${\mu}m$ channel length by micro contact printing (${\mu}$-CP) method. Patterning of micro-scale source/drain electrodes without etching was successfully achieved using silver nano particle ink, Polydimethylsiloxane (PDMS) stamp and FC-150 flip chip aligner-bonder. Sheet resistance of the printed Ag nano particle films were effectively reduced by two step annealing at $180^{\circ}C$.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.189-192
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• 2009

The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

• Proceedings of the Korea Concrete Institute Conference
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• 2004.11a
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• pp.723-726
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• 2004

Porous polymer concrete can be applied to roads, sidewalks, river embankment, drain pipes, conduits, retaining walls, yards, parking lots, plazas, interlocking blocks, etc. This study is to examine a content ratio of polypropylene fiber to improve bending strength, impact resistance and freezing and thawing rssistance of porous polymer concrete. Also, this study is performed to develop the porous polymer concrete using recycled coarse aggregate and blast furnace slag for application of structures needed permeability. At 7 days of curing, compressive strength, flexural strength, water permeability and flexural load are in the ragge of $17\~21MPa,\;5\~7MPa,\;4.1\times10^{-2}\~7.7\times10^{-2}cm/s$, respectively. It is concluded that the recycled aggregate can be used in the porous polymer concretes.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.220-225
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• 2018

A class E power oscillator is demonstrated for 6.78-MHz wireless power transfer system. The oscillator is designed with a class E power amplifier to use an LC feedback network with a high-Q inductor between the input and the output. Multiple capacitors are used to minimize the variation of the oscillation frequency by capacitance tolerance. The gate and drain bias voltages with opposite characteristics to make the frequency shift of the oscillator are connected in a resistance distribution circuit located at the output of the low drop-out regulator and supplied bias voltages for class E operation. The measured output of the class E power oscillator, realized using the co-simulation, shows 9.2 W transmitted power, 6.98 MHz frequency and 86.5% transmission efficiency at the condition with 20 V $V_{DS}$ and 2.4 V $V_{GS}$.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.775-778
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• 1987

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bais shows both positive and negative resistance characteristics depending on the gate threhold voltage and gate-to source bias voltage. In this study, the decision method of the internal temperature measurement by $V_{GS}$ and $V_{DS}$ are presented.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).