• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.232.2-232.2
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• 2013

본 연구에서는 asymmetric과 symmetric MOSFET 소자의 drain breakdown 및 snapback 특성을 분석하였다. 실험에서는 두 MOSFET 소자의 동작 영역에서 게이트와 드레인에 각각 전압을 인가하였다. 드레인 전류-전압 곡선으로 부터 drain breakdown 전압과 snapback 전압을 추출하였다. 결과 avalanche breakdown 발생 전의 드레인 전류는 asymmetric 구조의 경우 더 작은 값을 보였으며 이는 asymmetric 구조에서의 drain field 가 더 낮기 때문이다. 따라서 impact ionization은 asymmetric 구조에서 덜 발생하며, snapback 전압은 avalanche breakdown voltage가 작은 asymmetric 구조에서 크게 나타났다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.9
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• pp.1255-1259
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• 2013

A calculation method of the breakdown voltage for the Drain region with the spherical structure in high voltage analog CMOS is proposed. The Drain depletion region is divided into many sub-regions and the doping concentration of each sub-region is assumed to be constant. The field in each sub-region is calculated by the integration of the net charge and the breakdown voltage is calculated using the ionization integral method. The breakdown voltage calculated using the proposed method shows the maximum relative error of 3.3% compared with the result of the 2-dimensional device simulation using BANDIS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.12
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• pp.1872-1876
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• 2012

A calculation method of the breakdown voltage for the drain region with the cylindrical structure in LDMOS is proposed. The depletion region of the drain is divided into many smaller regions and the doping concentration of each split region is assumed to be uniformly distributed. The field and potential in each split region is calculated by the integration of the Poisson equation and the ionization integral method is used to compute the breakdown voltage. The breakdown voltage resulted from the proposed method shows the maximum relative error of 2.2% compared with the result of the 2-dimensional device simulation using BANDIS.

• Electrical & Electronic Materials
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• v.7 no.5
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• pp.376-382
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• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.159-165
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• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• Journal of the Semiconductor & Display Technology
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• v.12 no.3
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• pp.23-27
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.1
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• pp.18-22
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• 2005

We have proposed and fabricated a dual gate AlGaN/GaN high electron mobility transistor (HEMT), which exhibits the low leakage current and the high breakdown voltage for the high voltage switching applications. The additional gate between the main gate and the drain is specially designed in order to decrease the electric field concentration at the drain-side of the main gate. The leakage current of the proposed HEMT is decreased considerably and the breakdown voltage increases without sacrificing any other electric characteristics such as the transconductance and the drain current. The experimental results show that the breakdown voltage and the leakage current of proposed HEMT are 362 V and 75 nA while those of the conventional HEMT are 196 V and 428 nA, respectively.

• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.21-25
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

• Journal of the Korean Vacuum Society
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• v.22 no.6
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• pp.335-340
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• 2013

This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the $Si_3N_4$ passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.