• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.220-225
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• 2018

A class E power oscillator is demonstrated for 6.78-MHz wireless power transfer system. The oscillator is designed with a class E power amplifier to use an LC feedback network with a high-Q inductor between the input and the output. Multiple capacitors are used to minimize the variation of the oscillation frequency by capacitance tolerance. The gate and drain bias voltages with opposite characteristics to make the frequency shift of the oscillator are connected in a resistance distribution circuit located at the output of the low drop-out regulator and supplied bias voltages for class E operation. The measured output of the class E power oscillator, realized using the co-simulation, shows 9.2 W transmitted power, 6.98 MHz frequency and 86.5% transmission efficiency at the condition with 20 V $V_{DS}$ and 2.4 V $V_{GS}$.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• 한국전기전자재료학회논문지
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• 제11권5호
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.9-11
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• 2000

To increase the device linearities and the breakdown-voltages of FETs, Al$\sub$0.25/ Ga$\sub$0.75/AS / In$\sub$0.25/Ga$\sub$0.75/As / Partially doped channel FET(DCFET) structures are proposed. The metal- insulator -semiconductor (MIS) like structures show the high gate-drain breakdown voltage(-20 V) and high linearities. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.326-329
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• 2009

We investigated the degradation of $In_2O_3-Ga_2O_3$-ZnO (IGZO) thin-film transistors (TFTs), which is promising device for driving circuits of nextgeneration displays. We performed the electronic stress test by applying gate and drain voltage. We discussed the degradation mechanism by thermal analysis and device simulation.

• 한국통신학회논문지
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• 제22권8호
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• pp.1733-1739
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• 1997

An ultra-compact milimeter-wave broadband MMIC amplifier was designed using a direct-coupled topology combined with optimum feedback design. Significant reductionin the chip size was possible by employing the direct-coupled topology. Bias resistors required for the direct-coupled topology were also used as feedback elements. Feedback was optimized for millimeter-wave frequencies using reactive elements. The fabricated MMIC amplifier was realized in a chip size of 0.8mm$^{[-992]}$ and showed gains higher than 8 dB from 12 to 44 GHz. An output power of 30mW was achieved at 44 GHz with a drain efficiency of 10%.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Journal of Advanced Marine Engineering and Technology
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• 제30권8호
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• pp.901-906
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• 2006

In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.

• 한국전자파학회논문지
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• 제24권9호
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• pp.883-891
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• 2013

스마트폰 무선 충전 시나리오에서는 송신 패드에 비해 수신 패드의 크기가 작으므로 수신 패드의 위치에 상관없이 일정한 전력을 부하에 공급하는 것이 중요하다. 본 논문에서는 송신 패드와 수신 패드의 크기가 각각 $16cm{\times}18cm$와 $6cm{\times}8cm$의 직사각형 구조를 갖는 경우, 무선 전력 전송 송신부에 위치한 E급 증폭기의 Drain 바이어스 전압만을 조정하여 수신 패드의 위치에 상관없이 일정한 전력이 부하에 공급되는 방식을 제안하였다. 설계된 LF-대역 무선 전력 시스템의 구성은 PWM IC인 TL494로 제어되는 Buck converter 구조의 전원 회로, 저가의 IRF510 power MOSFET을 이용한 E급 증폭기, 송신 패드 및 수신 패드, 그리고 Schottky 다이오드를 이용한 풀 브릿지 정류기로 구성된다. 제작된 무선 전력 전송 시스템은 바이어스 조정을 하지 않는 경우 240 kHz에서 최대 4 W 출력과 67 % 이상의 시스템 효율을 가지며, 바이어스 조정을 하는 경우에는 수신 패드의 위치에 상관없이 수신 전력을 2 W로 일정하게 유지할 수 있다.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.1-7
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• 2006

본 논문에서는 자동 온도 보상 기법을 사용한 on-chip CMOS 내부 전원 전압 발생기를 제안하였다. PMOSFET의 경우, 게이트 바이어스 저압에 따라 온도의 변화에 대한 소오스-드레인간 전류 특성이 달라진다. 제안된 내부 전원 전압 발생기는 서로 다른 게이트 바이어스 전압에 두 개의 PMOSFET를 놓고, 이의 온도에 대한 서로 상이한 소오스-드레인간 전류 특성을 이용하여 내부 전원 전압 발생기 전체의 온도 의존도를 줄였다. 제안된 회로는 동부-아남 $0.18{\mu}m$ 공정을 이용하여 제작되었으며 측정 결과로 내부 전원 전압은 $-10^{\circ}C{\sim}100^{\circ}C$의 범위에서 $-0.49mV/^{\circ}C$의 온도 의존도를 보였으며 $2.2V{\sim}4.0V$의 동작 범위에서 외부 전압에 대하여 내부 전원 전압의 변화는 6mV/V를 나타내었다. 전체 전류소모는 $1.1{\mu}A@2.5V$로 저전력을 구현할 수 있었다.