• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.220-225
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• 2018

A class E power oscillator is demonstrated for 6.78-MHz wireless power transfer system. The oscillator is designed with a class E power amplifier to use an LC feedback network with a high-Q inductor between the input and the output. Multiple capacitors are used to minimize the variation of the oscillation frequency by capacitance tolerance. The gate and drain bias voltages with opposite characteristics to make the frequency shift of the oscillator are connected in a resistance distribution circuit located at the output of the low drop-out regulator and supplied bias voltages for class E operation. The measured output of the class E power oscillator, realized using the co-simulation, shows 9.2 W transmitted power, 6.98 MHz frequency and 86.5% transmission efficiency at the condition with 20 V $V_{DS}$ and 2.4 V $V_{GS}$.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.9-11
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• 2000

To increase the device linearities and the breakdown-voltages of FETs, Al$\sub$0.25/ Ga$\sub$0.75/AS / In$\sub$0.25/Ga$\sub$0.75/As / Partially doped channel FET(DCFET) structures are proposed. The metal- insulator -semiconductor (MIS) like structures show the high gate-drain breakdown voltage(-20 V) and high linearities. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.326-329
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• 2009

We investigated the degradation of $In_2O_3-Ga_2O_3$-ZnO (IGZO) thin-film transistors (TFTs), which is promising device for driving circuits of nextgeneration displays. We performed the electronic stress test by applying gate and drain voltage. We discussed the degradation mechanism by thermal analysis and device simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1733-1739
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• 1997

An ultra-compact milimeter-wave broadband MMIC amplifier was designed using a direct-coupled topology combined with optimum feedback design. Significant reductionin the chip size was possible by employing the direct-coupled topology. Bias resistors required for the direct-coupled topology were also used as feedback elements. Feedback was optimized for millimeter-wave frequencies using reactive elements. The fabricated MMIC amplifier was realized in a chip size of 0.8mm$^{[-992]}$ and showed gains higher than 8 dB from 12 to 44 GHz. An output power of 30mW was achieved at 44 GHz with a drain efficiency of 10%.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.8
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• pp.901-906
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• 2006

In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.9
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• pp.883-891
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• 2013

In wireless smart phone charging scenario, the transmitter pad is larger than the size of the receiver pad. Thus, it is important to supply a constant power to the receiver regardless of its location. In this paper, we propose a new method to regulate the receiver's power by adjusting a drain bias of class E power amplifier. The proposed LF-band wireless power transfer system is as follows: a buck converter power supply which is controlled by a pulse width modulation(PWM) IC TL494, a class E amplifier using a low cost IRF510 power MOSFET, a transmitter coil whose dimension is $16cm{\times}18cm$, a receiver coil whose dimension is $6cm{\times}8cm$, and a full bridge rectifier using Schottky diodes. A measured performance show a maximum output power of 4 W and system efficiency of 67 % if we fix the bias voltage. If we adjust the bias voltage, the received power can be maintained at a constant power of 2 W regardless of receiver pad location.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.