• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2326-2332
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.154-156
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.

• Transactions on Control, Automation and Systems Engineering
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• v.2 no.3
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• pp.163-168
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• 2000

The problems of mixed $H_2/H_{\infty}$ filtering design fer continuous and discrete time linear systems with time delay are investigated. The main purpose is to design a stable mixed $H_2/H_{\infty}$ filter which minimizes the H$_2$Performance measure satisfying a prescribed H$_{\infty}$ norm bound on the closed loop system in continuous-time case and discrete-time case, respectively. The sufficient conditions of existence of filter, the mixed $H_2/H_{\infty}$ filter design method, and the upper bound of performance measure are proposed by LMI(linear matrix inequality) techniques in terms of all finding variables. Also, we present optimization problems in order to get the optimal mixed $H_2/H_{\infty}$ filter in continuous and discrete time case, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.157-160
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• 1996

Physical systems axe generally continuous-time in nature. However as the data measured from these systems is generally in the form of discrete samples, and most modern signal processing is performed in the discrete-time domain, discrete-time models are employed. This paper describes methods for estimating the coefficients of continuous-time system within a closed loop control system. The method employs a recursive estimation algorithm to identify the coefficients of a discrete-time bilinear-operator model. The coefficients of the discrete-time bilinear-operator model closely approximate those of the corresponding continuous-time Laplace transform transfer function.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1165-1177
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• 2018

This paper investigates the active damping of grid-connected LCL filter resonance using high-pass filter (HPF) of the grid current. An expression for such HPF is derived in terms of the filter components. This expression facilitates a general study of the actively damped filter behavior in the discrete time domain. Limits for the HPF parameters are derived to avoid the excitation of unstable open loop poles since such excitation can reduce both the damping performance and the system robustness. Based on this study, straightforward co-design steps for the active damping loop along with the fundamental current regulator are proposed. A numerical example along with simulation and experimental results are presented to verify the theoretical analyses.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1286-1294
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• 2015

Capacitor current feedback active damping is extensively used in grid-connected converters with an LCL filter. However, systems tends to become unstable when the digital control delay is taken into account, especially in low switching frequencies. This paper discusses this issue by deriving a discrete model with a digital control delay and by presenting the stable region of an active damping loop from high to low switching frequencies. In order to overcome the disadvantage of capacitor current feedback active damping, this paper proposes a modified approach using grid current and converter current for feedback. This can expand the stable region and provide sufficient active damping whether in high or low switching frequencies. By applying the modified approach, the active damping loop can be simplified from fourth-order into second-order, and the design of the grid current loop can be simplified. The modified approach can work well when the grid impedance varies. Both the active damping performance and the dynamic performance of the current loop are verified by simulations and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.8
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• pp.996-1003
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• 1999

This paper propose a position-speed controller with an estimator which can estimate states and disturbance. The overall control system consists of two parts: the position-speed controller and an estimator. The Kalman filter applied as state-feedback controller is an optimal state estimator applied to a dynamic system that involves random perturbations and gives a linear, unbiased and minimum error variance recursive algorithm to optimally estimate the unknown state. Therefore, we consider the error problem about the servo system modeling and the measurement noise as a stochastic system and implement a optimal state observer, and enhance the estimate performance of position and speed using that. Using two-degree-of freedom(TDOF) conception, we design the command input response and the closed loop characteristics independently. The servo system is to improve the closed loop characteristics without affecting the command imput response. The characteristics of the closed loop system is improved by suppressing disturbance torque effectively with the disturbance observer using a inverse-transfer matrix. Therefore, the performance of overall position-speed controller is enhanced. Finally, the performance of the proposed controller is exemplified by some simulations and by applying the real servo system.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1587-1597
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• 2016

A novel active damping strategy for the LCL filter resonance is proposed using the grid current and the capacitor voltage. The proposed technique is deduced in the continuous time domain and a discussion for its discrete implementation is presented. According to the proposed technique, instability of the open loop system, which results in non-minimum phase behavior, can be avoided over wide range of resonant frequencies. Moreover, straightforward co-design steps for both the fundamental current regulator and the active damping loops can be used. A numerical example along with experimental results are introduced to validate the proposed strategy performance over wide range of resonant frequencies.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1659-1669
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• 2018

An improved circulating current suppression control method is proposed in this paper. In the proposed controller, an outer loop of the average capacitor voltage control model is used to balance the sub-module capacitor voltage. Meanwhile, an individual voltage balance controller and an arm voltage balance controller are also used. The DC and harmonic components of the circulating current are separated using a low pass filter. Therefore, a multiple quasi-proportional-resonant (multi-quasi-PR) controller is introduced in the inner loop to eliminate the circulating harmonic current, which mainly contains second-order harmonic but also contains other high-order harmonics. In addition, the parameters of the multi-quasi-PR controller are designed in the discrete domain and an analysis of the stability characteristic is given in this paper. In addition, a simulation model of a three-phase MMC system is built in order to confirm the correctness and superiority of the proposed controller. Finally, experiment results are presented and compared. These results illustrate that the improved control method has good performance in suppressing circulating harmonic current and in balancing the capacitor voltage.