• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1241-1246
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• 2005

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glich-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in 0,35um Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification the prototype error between DNL and INL is less than ${\pm}0.09LSB$ respectively. Also, fab-out chip was tested, analysed the cause of error operation, and proposed the field considerations for chip test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.12
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• pp.1923-1930
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• 2004

This paper presents digital microflow controllers(DMFC), where a fluidic digital-to-analog converter(DAC) is used to achieve high-linearity, fine-level flow control for applications to precision biomedical dosing systems. The fluidic DAC, composed of binary-weighted flow resistance, controls the flow-rate based on the ratio of the flow resistance to achieve high-precision flow-rate control. The binary-weighted flow resistance has been specified by a serial or a parallel connection of an identical flow resistor to improve the linearity of the flow-rate control, thereby making the flow-resistance ratio insensitive to the size uncertainty in flow resistors due to micromachining errors. We have designed and fabricated three different types of 4-digit DMFC: Prototype S and P are composed of the serial and the parallel combinations of an identical flow resistor, while Prototype V is based on the width-varied flow resistors. In the experimental study, we perform a static test for DMFC at the forward and backward flow conditions as well as a dynamic tests at pulsating flow conditions. The fabricated DMFC shows the nonlinearity of 5.0% and the flow-rate levels of 16(2$^{N}$) for the digital control of 4(N) valves. Among the 4-digit DMFC fabricated with micromachining errors, Prototypes S and P show 27.2% and 27.6% of the flow-rate deviation measured from Prototype V, respectively; thus verifying that Prototypes S and P are less sensitive to the micromachining error than Prototype V.V.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.882-885
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• 2003

In this paper, nonlinear echo cancellation using a correlation LMS (CLMS) algorithm is proposed to cancel the undesired nonlinear echo signals generated in the hybrid system of the telephone network. In the telephone network, the echo signals may result the degradation of the network performance. Furthermore, digital to analog converter (DAC) and analog to digital converter (ADC) may be the source of the nonlinear distortion in the hybrid system. The adaptive filtering technique based on the nonlinear Volterra filter has been the general technique to cancel such a nonlinear echo signals in the telephone network. But in the presence of the double-talk situation, the error signal for tap adaptations will be greatly larger, and the near-end signal can cause any fluctuation of tap coefficients, and they may diverge greatly. To solve a such problem, the correlation LMS (CLMS) algorithm can be applied as the nonlinear adaptive echo cancellation algorithm. The CLMS algorithm utilizes the fact that the far-end signal is not correlated with a near-end signal. Accordingly, the residual error for the tap adaptation is relatively small, when compared to that of the conventional normalized LMS algorithm. To demonstrate the performance of the proposed algorithm, the DAC of hybrid system of the telephone network is considered. The simulation results show that the proposed algorithm can cancel the nonlinear echo signals effectively and show robustness under the double-talk situations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.314-317
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• 2012

최근 차량의 멀티미디어 장치들이 증가하면서 이 장치들을 광 네트워크로 연결하여 멀티미디어 데이터를 송 수신해서 사용할 수 있는 MOST(Media Oriented Systems Transport) 네트워크를 적용한 차량들이 늘어나고 있다. MOST 네트워크는 최근 자동차 멀티미디어 시스템에 넓게 사용되고 있는 통신 시스템으로서, 동기 및 비동기 데이터를 동시에 전송할 수 있고, 최근에는 150Mbps를 전송할 수 있는 MOST150 네트워크를 이용한 연구가 활발히 진행되고 있다. 본 논문에서는 MOST150 네트워크에서 Audio 데이터 입출력을 제어하기 위한 알고리즘을 설계 및 구현하였다. Audio 데이터를 제어하는 방식은 ADC(Analog to Digital Converter)를 통해 Audio 데이터가 들어오면 IOC(IO Companion)를 통해 INIC으로 Audio데이터를 전달한다. INIC은 MOST150 네트워크로 데이터를 전송하고 그렇게 보내진 Audio 데이터를 MOST150 네트워크 내부의 다른 장치에서 INIC을 통해 데이터를 수신하여 DAC(Digital to Analog Converter)를 통해 Audio 장치에서 소리가 나는 것을 테스트하여 정상적으로 동작함을 확인하였다.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.