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A Novel Current Steering Cell Matrix DAC Architecture with Reduced Decoder Area  

Jeong, Sang-Hun (전북대학교 공과대학 전자정보공학부)
Shin, Hong-Gyu (원광대학교 공과대학 전기전자및정보공학부)
Cho, Seong-Ik (전북대학교 공과대학 전자정보공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.58, no.3, 2009 , pp. 627-631 More about this Journal
Abstract
This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.
Keywords
Current steering DAC; Cell matrix DAC;
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