• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Korean Journal of Optics and Photonics
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• v.8 no.5
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• pp.426-430
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• 1997

A signal processor is implemented to verify the possibility of a closed-loop signal processing for the open-loop fiber-optic gyroscope (FOG). As an all-digital implementation of phase tracking scheme, it does analog-to digital conversion of the detector output and signal processing all-digitally thereafter for a noise-immune FOG signal processor. It has a potential of 36-bits resolution in the $2\pi$ range which is best in the number and sets no limit in the magnitude of the phase shift. The new signal processor was tested on an all-fiber gyroscope and turned out to have a resolution of $3\mu$rad(corresponds to 0.74 deg/hr), which is good enough to measure the Earth's rotation rate.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.5
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• pp.333-340
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• 2003

Doppler processing is the heart of pulsed Doppler radar. It gives a clutter elimination and coherent integration. With the improvement of digital signal processors (DPSs), the implementation using them is more widely used in radar systems. Generally, so as for Doppler processor to process the input data in real time, a parallel processing concept using multiple DSPs should be used. This paper implements a programmable Doppler processor, which consists of MTI filter, DFB and square-law detector, using 8 ADSP21060s. Formulating the distribution time of the input data, the transfer time of the output data and the time required to compute each algorithm, it estimates total processing time and the number of required DSP. Finally, using the TSG that provides radar control pulses and simulated target signals, performances of the implemented Doppler processor are evaluated.

• Journal of Applied Reliability
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• v.8 no.2
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• pp.101-111
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• 2008

Good diagnostics improves both the safety and system unavailability of digital safety systems. The measure of a diagnostic capability is called the Coverage Factor. Because the Failure Modes, Effects and Diagnostic Analysis (FMEDA) provides information on the failure rates and failure mode distributions necessary to calculate a diagnostic coverage factor for a component, the FMEDA can be used as a useful tool to calculate it. Through performing FMEDA on a digital signal processor (DSP) board used in a digital safety system, it is shown that some components of the DSP board can be replaced or improved to satisfy the required diagnostic coverage. That is, the FMEDA can serve as a useful verification tool to design a diagnostic capability for the DSP board.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.5
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• pp.396-403
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• 2000

A thermal imaging system is implemented for the measurement and the analysis of the thermal distribution of the target objects. The main part of the system is a thermal camera in which a focal plane array typed sensor is introduced. The sensor detects the mid-range infrared spectrum of target objects and then it outputs a generic video signal which should be processed to form a frame thermal image. Here, a digital signal processor(DSP) is applied for the high speed processing of the sensor signals. The DSP controls analog-to-digital converter, performs correction algorithms and outputs the frame thermal data to frame buffers. With the frame buffers can be generated a NTSC signal and transferred the frame data to personal computer(PC) for the analysis and a monitoring of the thermal scenes. By performing the signal processing functions in the DSP the overall system achieves a simple configuration. Several experimental results indicate the performance of the overall system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.890-893
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• 2014

In this paper, we present a signal processing algorithm for a marine radar system, in which the evaluation of probability of collision as well as target detection and tracking are performed. Moreover, the digital signal processor that implements the algorithm is proposed. As simulation environment, a mechanically scanning antenna utilizing FMCW signal is used, conducting the beamforming operation with 1 degrees intervals. Test board consists of DSP chips and FPGA, which enable the implemented system to operate in real-time.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Korean Journal of Optics and Photonics
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• v.14 no.6
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• pp.588-593
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• 2003

A signal processor for interferometeric fiber optic sensors, which measure dynamic quantities of frequency up to 1 KHz with high sensitivity, is developed. It is a high-speed version of the all-digital phase tracking (ADPT) processor that was used to measure static or slowly-varying quantities. The processor was applied to a fiber optic Mach-Zehnder interferometer to evaluate the performance. The measured total harmonic distortion was near to -50 ㏈, which is the theoretical limit or the ADPT signal processing.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.592-601
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• 2004

The performance of active power filter depends on the inverter characteristic, the control method, and the accuracy of reference signal generator. The accuracy of reference signal generator is the most critical item to determine the performance of active power filter. This paper introduces a novel reference signal generator composed of improved adaptive predictive filter. The performance of proposed reference signal generator was verified by means of simulation with MATLAB. The application feasibility was evaluated by building and experimenting a single-phase active power filter based on the proposed reference generator, which was implemented in the DSP(digital signal processor) TMS320C31. Both simulation and experimental results confirm that the proposed reference signal generator can be utilized for the active power filter.