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Design and Implementation of Multi-mode Sensor Signal Processor on FPGA Device

다중모드 센서 신호 처리 프로세서의 FPGA 기반 설계 및 구현

  • Soongyu Kang (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Yunho Jung (Department of Smart Air Mobility, Korea Aerospace University)
  • 강순규 (한국항공대학교 항공전자정보공학과) ;
  • 정윤호 (한국항공대학교 스마트드론공학과)
  • Received : 2023.07.18
  • Accepted : 2023.07.30
  • Published : 2023.07.31

Abstract

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

Keywords

Acknowledgement

본 연구는 산업통상자원부의 기술혁신사업 (No.00144288, 00144290)의 일환으로 수행되었으며, CAD tool은 IDEC에 의해 지원되었음.

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