• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.671-672
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• 2011

지연소자를 이용하여 시간정보를 디지털 정보로 변환하는 회로를 설계하였다. 지연소자로는 아날로그 회로 혹은 디지털 회로로 구성할 수 있으나, 아날로그 지연소자의 경우 디지털 지연소자에 비해 공정 변화에 따른 신뢰성 면에서 우수한 특성을 가지므로 본 논문에서는 전류원 회로와 인버터를 이용하여 아날로그 형태로 지연소자를 구성하였다. 설계되어진 회로는 동작온도가 $-20^{\circ}C$에서 $70^{\circ}C$까지 변화하더라도 출력 특성의 변화가 없도록 설계되어졌으며, HSPICE 시물레이션을 이용하여 동작을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2004년도 춘계학술대회 논문집
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• pp.555-558
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• 2004

Due to the asymptotic property, deadbeat control can hardly applied to the continuous time system control. But some delay element method can deal such a problem. Except delay element method, well-known digital deadbeat control can br used with the aid of som smoothing elements. In this paper, and order smoothing element is used for the smoothing of the digital deadbeat controller. And this element is argumented to the plant, and so control problem is to control digitally the argumented system. We simulated this control system using Matlab language and finally apply this algorithm to the rotary inverted pendulum system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2593-2596
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• 2003

The deadbeat properties have been well known in designing digital control systems. But recently several researchers proposed a CDBC(Continuout-time DeadBeat Controller) in continuous time. They used delay or smoothing elements from the finite Laplace Transform. A delay element is made by the exponential terms. A smoothing element is used to smooth the digital control input. And eventually the process is argumentd with smoothing elements and then well-known digital deadbeat controller is designed Sometimes samplings are done in continuous time systems and some hold devices are used to relate to digital systems. So multirate sampling may enhance the efficiency of the CDBC. A DC servo motor is chosen for implementing CDBC algorithm. Especially Outputs according to the variable input and disturbance are simulated. by use of Matlab Simulink.

• 한국정밀공학회지
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• 제14권4호
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• pp.88-96
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• 1997

This paper suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteresis nonlinear element which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. A proper Lyapunov function is selected and the Lyapunov direct method is used to prove the asymptotic stability of the suggested control.

• 한국정보통신학회논문지
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• 제16권4호
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• pp.799-804
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• 2012

시간 정보를 디지털 정보로 변환하기 위한 아날로그 지연소자를 사용하는 시간-디지털 변환회로를 설계하였다. 설계된 회로는 동작 온도가 변화하더라도 안정된 출력을 얻을 수 있도록 설계하였으며, HSPICE 시뮬레이션을 통하여 동적을 확인하였다. 설계된 지연소자는 온도가 $-20^{\circ}C$에서 $70^{\circ}C$까지 변화할 때 상온에 비해 -0.18%-0.126%의 지연시간 변화율을 보였다. 그리고 이를 이용하는 시간-디지털 변환회로에서 온도가 $-20^{\circ}C$에서 $70^{\circ}C$까지 변화하고 디지털 출력 값이 15가 되었을 때의 시간을 비교하면, 상온에 비하여 -0.18%에서 0.12%의 시간차를 보였다. 그러나 온도 변화에 안정화되지 않은 시간-디지털 변환회로의 경우 상온에 비하여 -1.09%에서 1.28%의 시간차를 보였다.

• The Journal of the Acoustical Society of Korea
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• 제24권2E호
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• pp.38-45
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• 2005

The noise reduction of the In-The-Ear (ITE) hearing aid (HA) can be achieved by arrays of microphones. Each of the right and the left ears was assumed to have two HA microphones. These arrays of HA microphones produce particular patterns of directivity by some time delay between two microphones. The directivity pattern geometrically increase the S/N ratio. The boundary element method (BEM) was used for the three dimensional simulation of the HA directivity pattern with the two pairs' microphone arrays. The separation between two microphones was fixed to 10 mm. The time delay between the two microphones was calculated to produce the most narrow directivity pattern in the fore front of the head. The variation of the time delay was examined in accordance with input frequencies. This numerical analysis may be then applied for the calculation of the time delay parameter of the digital hearing aid DSP chip.