• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.671-672
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• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.555-558
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• 2004

Due to the asymptotic property, deadbeat control can hardly applied to the continuous time system control. But some delay element method can deal such a problem. Except delay element method, well-known digital deadbeat control can br used with the aid of som smoothing elements. In this paper, and order smoothing element is used for the smoothing of the digital deadbeat controller. And this element is argumented to the plant, and so control problem is to control digitally the argumented system. We simulated this control system using Matlab language and finally apply this algorithm to the rotary inverted pendulum system.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2593-2596
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• 2003

The deadbeat properties have been well known in designing digital control systems. But recently several researchers proposed a CDBC(Continuout-time DeadBeat Controller) in continuous time. They used delay or smoothing elements from the finite Laplace Transform. A delay element is made by the exponential terms. A smoothing element is used to smooth the digital control input. And eventually the process is argumentd with smoothing elements and then well-known digital deadbeat controller is designed Sometimes samplings are done in continuous time systems and some hold devices are used to relate to digital systems. So multirate sampling may enhance the efficiency of the CDBC. A DC servo motor is chosen for implementing CDBC algorithm. Especially Outputs according to the variable input and disturbance are simulated. by use of Matlab Simulink.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.4
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• pp.88-96
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• 1997

This paper suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteresis nonlinear element which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. A proper Lyapunov function is selected and the Lyapunov direct method is used to prove the asymptotic stability of the suggested control.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.799-804
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• 2012

To converter time information to digital information Time-to-Digital Converter(TDC) is designed by using analog delay elements. To obtain the temperature stable characteristics the circuit is designed and the operation of the designed circuit is confirmed by HSPICE. The characteristics variation of the designed delay element with temperature is from -0.18% to 0.126% compared to room temperature characteristics when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. Time difference is from -0.18% to 0.12% compared to room temperature characteristic when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. The time difference is simulated when the digital output is 15. However the time difference is from -1.09% to 1.28% in the TDC using temperature non-stable analog delay elements.

• The Journal of the Acoustical Society of Korea
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• v.24 no.2E
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• pp.38-45
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• 2005

The noise reduction of the In-The-Ear (ITE) hearing aid (HA) can be achieved by arrays of microphones. Each of the right and the left ears was assumed to have two HA microphones. These arrays of HA microphones produce particular patterns of directivity by some time delay between two microphones. The directivity pattern geometrically increase the S/N ratio. The boundary element method (BEM) was used for the three dimensional simulation of the HA directivity pattern with the two pairs' microphone arrays. The separation between two microphones was fixed to 10 mm. The time delay between the two microphones was calculated to produce the most narrow directivity pattern in the fore front of the head. The variation of the time delay was examined in accordance with input frequencies. This numerical analysis may be then applied for the calculation of the time delay parameter of the digital hearing aid DSP chip.