• Title/Summary/Keyword: device parameter

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Two-Dimensional Device Simulator TFT2DS for Hydrogenated Amorphous Silicon Thin Film Transistors (수소화된 비정질 실리콘 박막 트랜지스터의 이차원 소자 시뮬레이터 TFT2DS)

  • Choe, Jong-Seon;Neudeck, Gerold W.
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.1
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    • pp.1-11
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    • 1999
  • Hyrdogenated amorphous silicon thin film transistors are used as a pixel switching device of TFT-LCDs and very active research works on a-Si:H TFTs are in progress. Further development of the technology based on a-Si:H TFTs depends on the increased understanding of the device physics and the ability to accurately simulate the characteristics of them. A two-dimensional device simulator based on the realistic and flexible physical models can guide the device designs and their optimizations. A non-uniform finite-difference TFT Simulation Program, TFT2DS has been developed to solve the electronic transport equations for a-Si:H TFTs. In TFT2DS, many of the simplifying assumptions are removed. The developed simulator was used to calculate the transfer and output characteristics of a-Si:H TFTs. The measured data were compared with the simulated ones for verifying the validity of TFT2DS. Also the transient behaviors of a-Si:H TFTs were calculated even if the values of the related parameters are not accurately specified.

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Development and Evaluation of Tip Pinch Strength Measurement on a Paretic Hand Rehabilitation Device

  • Kim, Jung-Yeon;Cha, Ye-Rin;Lee, Sang-Heon;Jung, Bong-Keun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.2
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    • pp.1201-1216
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    • 2017
  • In this study, we described the development of a methodology to measure tip-pinch strength on the paretic hand rehabilitation device and aimed to investigate reliability of the device. FSR sensors were embedded on the device, and tip pinch strength was estimated with data collected from the sensors using a developed equation while participants were demonstrating tip pinch. Reliability tests included inter-rater, test-retest, and inter-instrument reliability. B&L Engineering pinch gauge was utilized for the comparison. Thirty-seven healthy students participated in the experiment. Both inter-rater and test-retest reliability were excellent as Intraclass Correlation Coefficients (ICCs) were greater than 0.9 (p<0.01). There were no statistically significant differences in tip-pinch strengths. Inter-instrument reliability analysis confirmed good correlation between the two instruments (r = 0.88, p < 0.01). The findings of this study suggest that the two instruments are not interchangeable. However, the tip-pinch mechanism used in the paretic hand rehabilitation device is reliable that can be used to evaluate tip pinch strength in clinical environment and can provides a parameter that monitors changes in the hand functions.

Design Parameter Structure for Architectural Elements of External Kinetic Facade

  • Ji, Seok-Hwan;Lee, Byung-Yun
    • KIEAE Journal
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    • v.16 no.3
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    • pp.35-46
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    • 2016
  • Purpose: This paper aims to analyse the composition system of architectural elements including shape, kinetic and material elements of kinetic facades and establish the design parameter system as a common conceptual and practical knowledge sharing platform with mechanical and electrical experts. Method: This research has been conducted in a three steps. At first, 120 cases of external shading devices are analyzed and their classification criteria have been established. Secondly geometric, kinetic and material elements are categorized in a common kinetic facade coordinates system considering environmental effects and operation method, and the applicability of combination of each element are tested. Lastly core design parameters for each element have been established in a common office building installation coordinate. Result: Geometry elements are categorized into seven geometric shapes and kinetic elements is categorized into basic linear and rotational motion and combinational folding and rolling motion. The combined set of parameters for three elements composes the whole design parameters for architectural elements of kinetic façade. Design parameters of shape elements are composed of shape, installation and arrangement parameters; design parameters for kinetic elements are composed of axis and range parameters; and design parameters of material elements are composed of thermal, lighting and color parameters.

A Study on the SPICE Model Parameter Extraction Method for the DC Model of the High Voltage MOSFET (High Voltage MOSFET의 DC 해석 용 SPICE 모델 파라미터 추출 방법에 관한 연구)

  • Lee, Un-Gu
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.12
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    • pp.2281-2285
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    • 2011
  • An algorithm for extracting SPICE MOS level 2 model parameters for the high voltage MOSFET DC model is proposed. The optimization method for analyzing the nonlinear data of the current-voltage curve using the Gauss-Newton algorithm is proposed and the pre-process step for calculating the threshold voltage and the mobility is proposed. The drain current obtained from the proposed method shows the maximum relative error of 5.6% compared with the drain current of 2-dimensional device simulation for the high voltage MOSFET.

Study on Thermal Characteristics of IGBT (IGBT의 열 특성에 관한 연구)

  • Kang, Ey-Goo;Ahn, Byoung-Sub;Nam, Tae-Jin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.70-70
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    • 2009
  • In this paper, we proposed 2500V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500V NPT IGBT according to size of device. In results, we obtaind design parameter with 375um n-drift thickness, 15um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000V NPT IGBT devices.

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A study on the circuit design for DC characteristic inspection of semiconductor devices (반도체 소자의 DC 특성 검사용 회로설계에 관한 연구)

  • 김준식;이상신;전병준
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.18 no.1
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    • pp.105-114
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    • 2004
  • In this paper, we design the circuits for DC parameter test of semiconductor devices. The DC parameter tester is the system which inspects the DC parameters of semiconductor devices. In the designed circuits, voltage(current) forcing current(voltage) sensing methods are used to inspect the parameters. The designed circuits are simulated by OR-CAD. The simulation results have good performance.

Development parameter measurement and profile analysis of electron beam resist for lithography simulation (리소그라피 모의실험을 위한 전자빔용 감광막의 현상 변수 측정과 프로파일 분석)

  • 함영묵;이창범;서태원;전국진;조광섭
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.198-204
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    • 1996
  • Electron beam lithography is one of the importnat technologies which can delineate deep submicron patterns. REcently, electron beam lithography is being applied in delineating the critical layers of semiconductor device fabrication. In this paper, we present a development simulation program for electron beam lithography and study the development profiles of resist when resist is exposed by the electron beam. Experimentally, the development parameter of positive and negative resists are measured and the data is applied to input parameter of the simulation program. Also simulation results are compared of the process results in the view of resist profiles. As a result, for PMMA and SAL 601 resist, the trend of simulation to the values of process parameters agree with real process results very well, so that the process results can be predicted by the simulation.

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Study on Design of 2500 V NPT IGBT (2500 V급 NPT-IGBT소자의 설계에 관한 연구)

  • Kang, Ey-Goo;Ahn, Byoung-Sub;Nam, Tae-Jin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.4
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    • pp.273-279
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    • 2010
  • In this paper, we proposed 2500 V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500 V NPT IGBT according to size of device. In results, we obtaind design parameter with 375 um n-drift thickness, 15 um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840 V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000 V NPT IGBT devices.

A study on parameter extraction for equivalent circuit model of RF silicon MOSFETs (RF용 Silicon MOSFET 등가회로 모델의 변수추출에 관한 연구)

  • 이성현;류현규
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.12
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    • pp.54-61
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    • 1997
  • An accurate extraction technique is developed to determine full euqivalent circuit parameters of Si MOSFETs using 1 set of measured S-parametes without complicated optimization process. This technique is based on the use of anlytic Z-parameters experessions for resistances and inductances and the Y-parameter ones for ntrinsic parameters. This accuracy is proved over the wide range of gate voltage by observing good agreement between measured and fitted Z-parameter equations and frequency-independent response of the extracted intrinsic parameters. Using this technique, gate voltage-dependencies of model parameters are obained in the saturation region and these results show the similar behavior to the short-channel effects expected from the device theory.

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LED 칩 열화특성에 적합한 열화모델 기반의 수명예측 시스템 구현

  • Yu, Gi-Hun;Lee, Jae-Hun;Kim, Dal-Seok;Lee, Mu-Seok;Yun, Yang-Gi;Han, Ji-Hun;Jang, Jung-Sun
    • Proceedings of the Korean Reliability Society Conference
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    • 2011.06a
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    • pp.79-85
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    • 2011
  • LED(Light Emitting Diode) is a powerful device used in applications as diverse as replacements for aviation lighting, automotive lighting as well as in traffic signals. This study is to propose a prediction system based on the degradation model of LED which is determined by combining scale and shape parameter. The degradation model is analysed goodness of fit test using calculated R-square, and is compared with previous models. A LED prediction system using degradation model is developed to automate estimations of degradation parameters and lifetimes.

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