• Journal of Applied Reliability
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• v.11 no.3
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• pp.267-279
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• 2011

LEDs have been used extensively in the mobile device, automobile, and general lighting because they are semi-permanent, long life, less power consumption, reliable and environmentally friendly. In this paper, the accelerated degradation test(ADT) for a general lighting 4W LED Lamp using external converter is considered. The conditions of ADT are high temperature and high humidity. We show that its life time is log-normally distributed with same parameters under both a normal condition and an accelerated condition, and also derive an accelerated factor.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Environmental Engineering Research
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• v.24 no.2
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• pp.318-323
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• 2019

Paper focuses on comparison between two different orifice plate configurations (plate number 1 and plate number 2) used as cavitating device in the hydrodynamic cavitation reactor for improving pollutant removal efficiencies. Effect of four different parameters such as hydraulic characteristics (in terms of range of flow rates, orifice velocities, cavitation number at different inlet pressures); cavitation number (in range of 5.76-0.35 for plate number 1 and 1.20-0.35 for plate number 2); inlet pressure (2-8 bars) and reaction time (0 to 60 min) in terms of chemical oxygen demand (COD) removal and chlorpyrifos degradation has been studied and compared. Optimum inlet pressure of 5 bars exists for degradation of pollutants for both the plates. It is found that geometry of orifice plate plays important role in removal efficiencies of pollutant. Results obtained confirmed that orifice plate 1 with configuration of 1.5 mm 17 holes; cavitational number of 1.54 performed better with around 60% COD and 98% chlorpyrifos removal as compared to orifice plate 2 having configuration of 2 mm single hole; cavitational number of 0.53 with 40% COD and 96% chlorpyrifos in 2 h duration time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1266-1272
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• 2012

An InGaZnO thin film transistor with different gate lengths and widths have been fabricated and their device degradations with device sizes have been also performed after negative gate bias stress. The threshold voltage and subthreshold swing have been decreased with decrease of gate length. However, the threshold voltages were increased with the decrease of gate lengths. The transfer curves were negatively shifted after negative gate stress and the threshold voltage was decreased. However, the subthreshold swing was not changed after negative gate stress. This is due to the hole trapping in the gate dielectric materials. The decreases of the threshold voltage variation with the decrease of gate length and the increase of gate width were believed due to the less hole injection into gate dielectrics after a negative gate stress.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.12-17
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• 2001

It is shown in the present study that during the HTS (hot temperature storage) test, the metal contamination by impure elements can be highly susceptible to the void formation, leading to the open failure of the power line in the memory device. Such a functional failure associated with the metal contamination was investigated to be dominant in the early stages of the HTS test while the formation of a stress-driven void is mainly observed in the later stages. In particular, it was found that the void formed in the contaminated metal takes on a slit-like shape which has been known to be characteristic of the stress-related voiding. The impure elements leading to the metal degradation were identified to be carbon and oxygen introduced during the metal sputtering process. The experimental works show that the device reliability was significantly improved by reducing the level of such impure elements within metal. It is shown in the present study that during the HTS (hot temperature storage) test, the metal contamination by impure elements can be highly susceptible to the void formation, leading to the open failure of the power line in the memory device. Such a functional failure associated with the metal contamination was investigated to be dominant in the early stages of the HTS test while the formation of a stress-driven void is mainly observed in the later stages. In particular, it was found that the void formed in the contaminated metal takes on a slit-like shape which has been known to be characteristic of the stress-related voiding. The impure elements leading to the metal degradation were identified to be carbon and oxygen introduced during the metal sputtering process. The experimental works show that the device reliability was significantly improved by reducing the level of such impure elements within metal.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.377-382
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• 2010

With the advent of flash memory based new storage device (SSD), there is considerable interest within the computer industry in using flash memory based storage devices for many different types of application. The dynamic index structure of large text collections has been a primary issue in the Information Retrieval Applications among them. Previous studies have proven the three approaches to be effective: In- Place, merge-based index structure and a combination of both. The above-mentioned strategies have been researched with the traditional storage device (HDD) which has a constraint on how keep the contiguity of dynamic data. However, in case of the new storage device, we don' have any constraint contiguity problems due to its low access latency time. But, although the new storage device has superiority such as low access latency and improved I/O throughput speeds, it is still not well suited for traditional dynamic index structures because of the poor random write throughput in practical systems. Therefore, using the experimental performance evaluation of various index maintenance schemes on the new storage device, we propose an efficient index structure for new storage device that improves significantly the index maintenance speed without degradation of query performance.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.1
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• pp.34-39
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• 2006

In high-voltage devices such as thyristor, beveling is mostly used junction termination method to reduce the surface electric field far below the bulk electric field and to expand the depletion region thus that breakdown occurs in the bulk of the device rather than at the surface. However, coating material used to protect the surface of the device contain so many charges which affect the electrical characteristics of the device. And device reliability is also affected by this charge. Therefore, it is needed to analyze the effect of surface charge on electrical characteristics of the device. In this paper, we analyzed the breakdown voltage and leakage current characteristics of the thyristor as a function of the amount of surface charge density. Two dimensional process simulator ATHENA and two-dimensional device simulator ATLAS is used to analyze the surface charge effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

• Progress in Superconductivity and Cryogenics
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• v.25 no.2
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• pp.14-18
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• 2023

Superconducting layers deposited on the metal substrate using the pulsed laser deposition process (PLD) play a crucial role in exploring new applications of superconducting wires and enhancing the performance of superconducting devices. In order to improve the superconducting property and increase the throughput of superconducting wire fabricated by pulsed laser deposition, high temperature heating device is needed that provides high temperature stability and strong durability in high oxygen partial pressure environments while minimizing performance degradation caused by surface contamination. In this study, new heating device have been developed for PLD process that deposit and growth the superconducting material continuously on substrate using reel-to-reel transportation apparatus. New heating device is designed and fabricated using iron-chromium-aluminum wire and alumina tube as a heating element and sheath materials, respectively. Heating temperature of the heater was reached over 850 ℃ under 700 mTorr of oxygen partial pressure and is kept for 5 hours. The experimental results confirm the effectiveness of the developed heating device system in maintaining a stable and consistent temperature in PLD. These research findings make significant contributions to the exploration of new applications for superconducting materials and the enhancement of superconducting device performance.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.535-538
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• 2005

We report the influence of the threshold voltage and mobility fluctuation in TFT on current mode digital circuit performance. We found that the threshold voltage showed more serious circuit malfunction. We studied new circuit configuration for improvement.