• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.685-691
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• 2001

본 논문은 4단계 파이프 라인과 VLIW (Very Long Instruction Word) 구조를 갖는 FLOVA라는 DSP 프로세서의 테스트용이 설계 기법을 다룬다. Full-scan design, BIST(Built-In-Self-Test), IEEE 1149.1의 기법들이 플립플롭과 floaing point unit, 내장된 메모리, I/O cell 등에 각각 적용되었다. 이러한 기법들은 테스트 용이도의 관점에서 FLOVA의 구조에 적절하게 적용되었다. 본 논문에서는 이와 같이 FLOVA에 적용된 테스트 용이 설계의 특징들을 중심으로 상세하게 기술한다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.329-334
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• 2002

For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.517-526
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• 1987

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.475-477
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• 2001

프레임웍의 결함들을 효과적으로 발견하기 위해서는 테스트 실행 과정 중에서 결함들이 민감하게 감응하여 결함으로 인한 오동작의 흔적이 남겨질 수 있어야 한다 그런데 프레임웍은 개조, 합성된 확장 부위에 결합되는 후크 클래스(hook class)들의 시험에 대한 제어와 관찰이 어려운 성실을 가지고 있다. 이를 해결하기 위해 프레임웍의 정상동작 여부를 판단하는데 단서가 되는 자료(clue data)를 포착하여 외부로 드러내는 기능을 수행하는 테스트 센서타이저를 설계하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.54-61
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.26-33
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• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.18-24
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• 2011

A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1963-1964
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• 2008

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. We propose a new technique to re-design about clock operation. This technique propose about low power operation of scan clock and saved time of test operation.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.