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An Efficient Non-Scan DFT Scheme for Controller Circuits  

Shim, Jae-Hun (Department of Computing, Graduate School, Soongsil University)
Kim, Moon-Joon (Department of Computing, Graduate School, Soongsil University)
Park, Jae-Heung (Department of Computing, Graduate School, Soongsil University)
Yang, Sun-Woong (Department of Computing, Graduate School, Soongsil University)
Chang, Hoon (School of Computing, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.11, 2003 , pp. 54-61 More about this Journal
Abstract
In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.
Keywords
Non-Scan DFT; Fault Efficiency; FSM; Controllability; Obversability;
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