• Title/Summary/Keyword: design-for-testability(DFT)

Search Result 17, Processing Time 0.027 seconds

A New RF Test Circuit on a DFT Technique (DFT 방법을 위한 새로운 고주파 검사 회로)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2006.05a
    • /
    • pp.902-905
    • /
    • 2006
  • This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides input impedance. gain, noise figure. input voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by output DC voltages from the DR chip.

  • PDF

On-Chip Design-for-Testability Circuit for RF System-On-Chip Applications (고주파 시스템 온 칩 응용을 위한 온 칩 검사 대응 설계 회로)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.15 no.3
    • /
    • pp.632-638
    • /
    • 2011
  • This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

A Non-Scan Design-For-Test Technique for RTL Controllers/Datapaths based on Testability Analysis (RTL 회로를 위한 테스트 용이도 기반 비주사 설계 기법)

  • Kim, Sung-Il;Yang, Sun-Woong;Kim, Moon-Joon;Park, Jae-Heung;Kim, Seok-Yoon;Chang, Hoon
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.30 no.2
    • /
    • pp.99-107
    • /
    • 2003
  • This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.

A Study on Insuring the Full Reliability of Finite State Machine (유한상태머신의 완벽한 안정성 보장에 관한 연구)

  • Yang Sun-Woong;Kim Moon-Joon;Park Jae-Heung;Chang Hoon
    • Journal of Internet Computing and Services
    • /
    • v.4 no.3
    • /
    • pp.31-37
    • /
    • 2003
  • In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.

  • PDF

Disign Technique and Testability Analysis of High Speed Full-Swing BiCMOS Circuits (테스트가 용이한 고속 풀 스윙 BiCMOS회로의 설계방식과 테스트 용이도 분석)

  • Lee, Jae Min;Jung, Kwang Sun
    • Journal of the Korean Society of Industry Convergence
    • /
    • v.4 no.2
    • /
    • pp.199-205
    • /
    • 2001
  • With the growth of BiCMOS technology in ASIC design, the issue of analyzing fault characteristics and testing techniques for BiCMOS circuits become more important In this paper, we analyze the fault models and characteristics of high speed full-swing BiCMOS circuits and the DFT technique to enhance the testability of full-swing high speed BiCMOS circuits is discussed. The SPICE simulation is used to analyze faults characteristics and to confirm the validity of DFT technique.

  • PDF

ALU Design & Test for 32-bit DSP RISC Processors (32비트 DSP RISC 프로세서를 위한 ALU 설계 및 테스트)

  • 최대봉;문병인
    • Proceedings of the IEEK Conference
    • /
    • 1998.10a
    • /
    • pp.1169-1172
    • /
    • 1998
  • We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

  • PDF

An Efficient Non-Scan DFT Scheme for Controller Circuits (제어 회로를 위한 효율적인 비주사 DFT 기법)

  • Shim, Jae-Hun;Kim, Moon-Joon;Park, Jae-Heung;Yang, Sun-Woong;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.40 no.11
    • /
    • pp.54-61
    • /
    • 2003
  • In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.

On a Design and Implementation Technique of a Universal ATPG for VLSI Circuits (VLSI 회로용 범용 자동 패턴 생성기의 설계 및 구현 기법)

  • Jang, Jong-Gwon
    • The Transactions of the Korea Information Processing Society
    • /
    • v.2 no.3
    • /
    • pp.425-432
    • /
    • 1995
  • In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.

  • PDF

New Programmable RF DFT Circuit for Low Noise Amplifiers (LNA를 위한 새로운 프로그램 가능 고주파 검사용 설계회로)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.44 no.4
    • /
    • pp.28-39
    • /
    • 2007
  • This paper presents a programmable RF DFT (Radio Frequency Design-for-Testability) circuit for low noise amplifiers. We have developed a new on-chip RF DFT circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements [1, 2]. This circuit is extremely useful for today's RFIC devices in a complete RF transceiver environment. The DFT circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip DFT circuit can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz low noise amplifiers for GSM, Bluetooth and IEEE802.11g standards. The circuit is simple and inexpensive.

A Review of Structural Testing Methods for ASIC based AI Accelerators

  • Umair, Saeed;Irfan Ali, Tunio;Majid, Hussain;Fayaz Ahmed, Memon;Ayaz Ahmed, Hoshu;Ghulam, Hussain
    • International Journal of Computer Science & Network Security
    • /
    • v.23 no.1
    • /
    • pp.103-111
    • /
    • 2023
  • Implementing conventional DFT solution for arrays of DNN accelerators having large number of processing elements (PEs), without considering architectural characteristics of PEs may incur overwhelming test overheads. Recent DFT based techniques have utilized the homogeneity and dataflow of arrays at PE-level and Core-level for obtaining reduction in; test pattern volume, test time, test power and ATPG runtime. This paper reviews these contemporary test solutions for ASIC based DNN accelerators. Mainly, the proposed test architectures, pattern application method with their objectives are reviewed. It is observed that exploitation of architectural characteristic such as homogeneity and dataflow of PEs/ arrays results in reduced test overheads.