• Title/Summary/Keyword: design bias

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Characterization of Channel Electric Field in LDD MOSFET (LDD MOSFET 채널 전계의 특성해석)

  • Park, Min-Hyoung;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1988.11a
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    • pp.363-367
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    • 1988
  • A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

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Design and fabrication of GaAs MMIC VCO/Mixer for PCS applications (PCS영 GaAs VCO/Mixer MMIC 설계 및 제작에 관한 연구)

  • 강현일;오재응;류기현;서광석
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.5
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    • pp.1-10
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    • 1998
  • A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

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Design and Analysis of a Permanent Magnet Biased Magnetic Levitation Actuator (영구자석 바이어스 자기부상 구동기 설계 및 해석)

  • Na, Uhn Joo
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.26 no.7
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    • pp.875-880
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    • 2016
  • A new hybrid permanent magnet biased magnetic levitation actuator (maglev) is developed. This new maglev actuator is composed of two C-core electromagnetic cores separated with two permanent magnets. Compared to the conventional hybrid maglev actuators, the new actuator has unique flux paths such that bias flux paths are separated with control flux paths. The control flux paths have minimum reluctances only developed by air gaps, so the currents to produce control fluxes can be minimized. The gravity load can be compensated with the permanent magnet bias fluxes developed at off-centered air gap positions while external disturbances are controlled with control fluxes by currents. The consumed power to operate this levitation system can be minimized. 1-D magnetic circuit model is developed for this model such that the flux densities and magnetic forces are extensively analyzed. 3-D finite element model is also developed to analyze the performances of the maglev actuator.

Current Control Type Pulse Width Modulation by Using Pair Transistor Circuit (쌍트란지스터 회로에 의한 전류제어형 펄스변조)

  • 오현위
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.8 no.4
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    • pp.7-16
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    • 1971
  • A negative resistance element in the form of current control can be obtained by using a pair transistor circuit. This negative resistance element can be used in the generation of square pulse, and also in the realization of pulse width modulation circuit by superposing signal current on its bias current. The each bias current of pair circuit increases alternatively according to the polarity of the input signal. In order to satisfy this condition, a modified full wave rectification circuit has been adopted for supplying the input signal. Theoritical analysis of pulse times and design guidances for practical modulation circuit parameters are presented.

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Target State Estimator Design Using FIR filter and Smoother

  • Kim, Jae-Hun;Joon Lyou
    • Transactions on Control, Automation and Systems Engineering
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    • v.4 no.4
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    • pp.305-310
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    • 2002
  • The measured rate of the tracking sensor becomes biased under some operational situation. For a highly maneuverable aircraft in 3D space, the target dynamics changes from time to time, and the Kalman filter using position measurement only can not be used effectively to reject the rate measurement bias error. To cope with this problem, we present a new algorithm which incorporate FIR-type filter and FIR-type fixed-lag smoother, and demonstrate that it has the optimal performance in terms of both estimation accuracy and response time through an application example to the anti-aircraft gun fire control system(AAGFCS).

A Current-controlled CMOS operational transconductance amplifier (전류- 제어 CMOS operational transconductance amplifier)

  • Chung, W.S.;Cha, H.W.;Kim, H.B.;Rho, S.R.
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.563-566
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    • 1988
  • A current-controlled CMOS operational transconductance amplifier(OTA), whose transconductance is directly proportional to the DC bias current, has been developed for many electronic circuit applications. It features that its transconductance is insensitive to temperature unlike that of the bipolar OTA. This property makes it possible to use the proposed OTA as a basic buliding block in electrically variable circuit design. The SPICE simulation shows that the conversion sensitivity of the circuit is 44.62 mv /${\mu}A$ and the linearity error less than 0.54 % over a bias current range from 2 ${\mu}A$ to 120 ${\mu}A$ when the output is loaded with a 1${\Omega}$ resistor.

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Equivalent Noise Charge Measurements in Hydrogenated Amorphous Silicon Radiation Detectors

  • Kim, Ho-Kyung;Hur, Woo-Sung;Gyuseong Cho
    • Proceedings of the Korean Nuclear Society Conference
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    • 1995.05a
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    • pp.973-979
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    • 1995
  • The input equivalent noise charge (ENC) of hydrogenated amorphous silicon radiation detector diodes was measured and analyzed. The noise sources of amorphous silicon diodes were analyzed into three sources; shot noise, flicker noise and thermal noise from the contact resistance. By comparing the measured ENC with the calculated signal charge in uniform generation case, the signal-to-noise ratio (S/N) for the sample diodes is estimated as a function of the detector bias and the shaping time of Gaussian pulse shaper. The maximum S/N occurred at the bias level just above the full depletion voltage for shaping time of 2∼3 ${\mu}$sec. The developed method is useful in optimum design or amorphous silicon p-i-n diodes for charged particulate radiation spectroscopy.

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Design of Broadband 12GHz Active Frequency Multiplier (광대역 특성을 갖는 12GHz 능동 주파수 체배기 설계)

  • Jeon, Jong-Hwan;Kim, Tae-Yong;Choi, Won;Oh, Chung-Gyun;Koo, Kyung-Heon
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.72-76
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    • 2003
  • In this paper, active frequency doubler with broadband characteristics and unconditional stability from 6GHz to 12GHz was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed RC circuit between bias line and input matching network for the improvement of stability. With 0dBm input power, second harmonic of 1.7dBm at 12GHz, - 27.5dBc suppression of 6GHz fundamental, -18dBc suppression of 18GHz 3rd harmonic and the output bandwidth of 1.8GHz have been measured.

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2.4GHZ CMOS LC VCO with Low Phase Noise

  • Qian, Cheng;Kim, Nam-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.501-503
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    • 2008
  • This paper presents the design of a 2.4 GHz low phase noise fully integrated LC Voltage-Controlled-Oscillator (VCO) in $0.18{\mu}m$ CMOS technology. The VCO is without any tail bias current sources for a low phase noise and, in which differential varactors are adopted for the symmetry of the circuit. At the same time, the use of differential varactors pairs reduces the tuning range, i.e., the frequency range versus VTUNE, so that the phase noise becomes lower. The simulation results show the achieved phase noise of -138.5 dBc/Hz at 3 MHz offset, while the VCO core draws 3.9mA of current from a 1.8V supply. The tuning range is from 2.28GHz to 2.55 GHz.

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Design of a Rceiver MMIC for the CDMA Terminal (CDMA 단말기용 수신단 MMIC 설계)

  • 권태운;최재하
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.1
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    • pp.65-70
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    • 2001
  • This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

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