• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.201-210
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• 2018

This paper proposes a new start-up method for a load commutated inverter (LCI) in a large synchronous gas-turbine generator. The initial rotor position for start-up torque is detected by the proposed initial angle detector, which consists of an integrator and a phase-locked loop. The initial rotor position is accurately detected within 150ms, and the angle difference between the real position and the detected position is less than 1%. The LCI system operates in two modes (forced commutation mode and natural commutation mode) according to operating speed range. The proposed controllers include a forced commutation controller for the low-speed range, a PI speed controller and a PI current controller, where the forced commutation controller is connected to the current controller in parallel. The current controller is modeled by Matlab/Simulink, where a six-pulse delay of the thyristor and a processing delay are considered by using a zero-order hold. The performance of the proposed start-up method is evaluated in Matlab/Psim at standstill and at low speed. To verify the feasibility of the method, a 5kVA LCI system prototype is implemented, and the proposed initial angle detector and the system performance are confirmed by experimental results from standstill to 900rpm.

• Journal of Power Electronics
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• 제10권4호
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• 한국통신학회논문지
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• 제26권12A호
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• pp.2000-2011
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• 2001

본 논문에서는 기존 1배속 및 6배속과 같은 저속 DVD 시스템에서 설계되었던 Analog PLL(Phase Locked Loop)을 고배속 동작에 유용하게 디지털화 했으며, 고속인 20배속 DVD 시스템에서의 최적 Digital PLL 모델을 제시하였다. 특히, 고속 DVD 시스템 설계에서 성능 열화의 주요 원인인 bulk delay, 샘플링 클럭 주파수 오타, 비대칭 신호 현상과 같은 채널 영향들을 고려하여 안정적으로 동작할 수 있는 DPLL 설계에 초점을 맞추었다. 우선, DPLL에서는 새로운 타이밍 에러 검출 알고리즘으로 변형된 Early-Late 방법을 제시하였다. 그리고, 비대칭 신호 보정기에는 고속으로 동작하고 안정적으로 보정 역할을 수행하는 영점교차 지점을 이용한 4샘플 신호 보정 알고리즘을 설계하였다. 본 논문에서 제안하는 타이밍 에러 검출기는 기존 방식에 비해 각각, 3dB의 SNR 이득과 지터성능이 4배 향상됨을 볼 수 있었고 또한, 영점교차 지점에서 4샘플 신호를 이용한 보정 알고리즘은 기존 방식에 비해 보상시간의 50% 단축과 2dB의 SNR 이득, 지터 성능의 34% 효율을 볼 수 있었다. 최종적으로 제안된 비대칭 보정기와 DPLL이 통합된 시스템을 BER 성능 평가를 통해서 기존 알고리즘에 비해 제안된 방식이 0.4dB, 2dB 성능 향상을 확인하였다.

• 전자공학회논문지
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• 제50권10호
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• pp.98-104
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• 2013

본 논문에서는 무선 통신 및 근거리 위치 인식이 가능한 WBAN(wireless body area network) 용 UWB(Ultra-wide band) 수신기 회로를 제안한다. UWB 수신기는 에너지 검출 방식의 OOK(on-off keying) 변조가 가능하도록 설계가 되었다. 고속의 sampling 을 하기 위해서 4bit ADC 는 DLL(delay locked loop) 을 이용하여 sub-sampling 기법을 사용하도록 설계되었다. 제안된 UWB 수신기는 CMOS $0.18{\mu}m$ 공정을 이용하여 설계되었으며, 전원 전압 1.8V에서 61mA의 전류를 소모하면서 -85.7dBm의 수신 감도, 42.1dB의 RF front-end 게인, 3.88 dB의 noise figure, 최대 4m 까지의 거리 감지 성능을 가지고 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Journal of Power Electronics
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• 제10권2호
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• pp.203-209
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• 2010

This paper describes the development of a three-phase line-interactive DVR with a new sag detection algorithm. The developed detection algorithm has a hybrid structure composed of an instantaneous detector and RMS-variation detectors. The source voltage passes through the sliding-window DFT and RMS calculator, and the instantaneous sag detector. If an instantaneous sag is detected, the RMS variation detector-1 is selected to calculate the RMS variation. The RMS variation detector-2 is selected when the instantaneous sag occurs under the operation of the RMS variation detector-1. The feasibility of the proposed algorithm is verified through computer simulations and experimental work with a prototype of a line-interactive DVR with a 3kVA rating. The line-interactive DVR with the proposed algorithm can compensate for an input voltage sag or an interruption within a 2ms delay. The developed DVR can effectively compensate for a voltage sag or interruption in sensitive loads, such as computers, communications equipment, and automation equipment.

• Journal of Electrical Engineering and Technology
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• 제6권5호
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• Journal of Power Electronics
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• 제19권2호
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• pp.487-496
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• 2019

For a solid-state transformer (SST), some factors, such as signal delay, switching loss and differences in the system parameters, lead to unbalanced DC-link voltages among the cascaded H-bridges (CHB). With a control method implemented in the ${\alpha}{\beta}$ frame, the DC-link voltages are balanced, and the reactive power is equally distributed among all of the H-bridges. Based on the ${\alpha}{\beta}$ frame control, the system can achieve independent active current and reactive current control. In addition, the control method of the high-voltage stage is easy to implement without decoupling or a phase-locked loop. Furthermore, the method can eliminate additional current delays during transients and get the dynamic response rapidly without an imaginary current component. In order to carry out the controller design, the vector refactoring relations that are used to balance DC-link voltages are derived. Different strategies are discussed and simulated under the unbalanced load condition. Finally, a three-cell CHB rectifier is constructed to conduct further research, and the steady and transient experimental results verify the effectiveness and correctness of the proposed method.

• 대한전자공학회논문지SD
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• 제48권2호
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• pp.7-13
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• 2011

본 논문에서는 디지털 위상고정루프(All-digital PLL)를 구성하는 핵심 블록인 시간-디지털 변환기(Time-to-Digital Converter)를 제안하고 구현하였다. 본 연구에서는 게이티드 링 오실레이터 시간-디지털 변환기(GRO-TDC)의 기본 구조에 버니어 지연단(VDL)을 이용하여 다중 위상을 얻음으로써 보다 높은 해상도를 얻을 수 있는 구조를 제안하였다. 게이티드 링 오실레이터(GRO)는 총 7개의 지연셀을 사용하였고, 버니어 지연단(VDL) 3단을 이용하여 총 21개의 다중 위상을 사용하여 시간-디지털 변환기(TDC)를 설계하였다. 제안한 회로는 $0.13{\mu}m$ 1P-6M CMOS 공정을 사용하여 설계 및 구현하였다. 측정결과, 제안한 시간-디지털 변환기(TDC)의 최대 입력 주파수는 100MHz이고, 해상도는 26ps로 측정되었으며, 출력은 8-비트이며, 검출이 가능한 최대 위상 차이는 5ns의 위상 차이까지 검출이 가능하였다. 전력 소비는 측정된 Enable 신호의 크기에 따라 최소 8.4mW에서 최대 12.7mW로 측정되었다.