• ETRI Journal
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• v.36 no.2
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• pp.214-223
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• 2014

A fully-integrated penta-band reconfigurable power amplifier (PA) is developed for handset Tx applications. The output structure of the proposed PA is composed of the fixed output matching network, power and frequency reconfigurable networks, and post-PA distribution switches. In this work, a new reconfiguration technique is proposed for a specific band requiring power and frequency reconfiguration simultaneously. The design parameters for the proposed reconfiguration are newly derived and applied to the PA. To reduce the module size, the switches of reconfigurable output networks and post-PA switches are integrated into a single IC using a $0.18{\mu}m$ silicon-on-insulator CMOS process, and a compact size of $5mm{\times}5mm$ is thus achieved. The fabricated W-CDMA PA module shows adjacent channel leakage ratios better than -39 dBc up to the rated linear power and power-added efficiencies of higher than around 38% at the maximum linear output power over all the bands. Efficiency degradation is limited to 2.5% to 3% compared to the single-band reference PA.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.463-467
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• 2000

In this paper, the new LIGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The Simulations are performed in order to investigate the effects of the positiion, whidth and concentration of trap injection region with a reduced minority carrier lifetime using 2D device simulator MEDICI. Their electrical characteristics are analyzed and the optimum design parameters are extracted. As a result of simulation, the turn off time for the model A with the trap injection is $0.78\mus$. These results indicate the improvement of about 2 times compared with the conventional SOI LIGBT because trap injection prevents minority carriers which is stored in the n-drift region during turn off switching. The latching current is $1.5\times10^{-4}A/\mum$ and forward blocking voltage is 168V which are superior to those of conventional structure. It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.412-413
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• 2005

This paper describes resonant frequency of the structural behavior of micro-cantilever beam simulated by FEM (Finite Element Method). The resonant characteristics and the sensitivity of cantilever-shaped SOI resonant were measured for the application of chemical sensor. The resonant frequency of the fabricated micro-cantilever system was found to be 5.59kHz when the size of cantilever is $500{\mu}m$ long, $100{\mu}m$ wide and $1{\mu}m$ thick. Generation of resonant frequency measured by Modal Analysis is resulted in length of cantilever. The length was found to be a dominant factor for the selection of required resonant frequency range. On the other side, the width had influenced very little on either the magnitude of resonant frequency or the sensitivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1567-1570
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• 2022

This paper, we presents a RF protection technique of antenna switch by improving the power handling capability in worst case environment mode for mobile phone applications without critical payment of circuit performances such as insertion loss, isolation and ACBV (AC breakdown voltage). By applying a additional capacitive path located in front of the antenna in cell-phone, it performs the effective reduction of input power in high voltage standing wave ratio (VSWR) condition. Under the all-path off condition which causes a high VSWR, it achieved 37.7dBm power handling level as high as 5.7dB compared to that of conventional one at 2GHz. In addition, insertion loss and isolation performances were 0.31dB and 42.72dB at 2 GHz, respectively which were almost similar to that of the conventional circuit. The proposed antenna switch was fabricated in 130nm CMOS SOI technology.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.467-468
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• 2006

In this work, we present the comparison between $d_{31}\;and\;d_{33}$ mode characterization using the PZT micro-actuator for large displacement. The PZT micro-actuator consisted of Si, PZT, and Pt layer on SOI wafer. The electrode shapes were laminated and interdigitated for $d_{31}\;and\;d_{33}$ mode, respectively. In order to characterize the actuation mode, we measured the displacement using laser interferometer. The maximum displacement of d31 mode was $12.2{\mu}m$ at 10V, the actuation characterization of d31 was better than that of d33 mode. We estimated that displacement of d33 mode would be larger than that of d31 above 30V.

• Journal of Korean Philosophical Society
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• v.131
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• pp.303-330
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• 2014

Les avis des philosophes sur la mort sont $diff{\acute{e}}rentes$ selon leurs visions du monde. Certains essaient de surmonter la peur sur la mort, en $n{\acute{e}}gligeant$ la mort, et certains essaient de vivre le vraie vie par la $m{\acute{e}}ditation$ de la mort. Chez Kierkegaard la notion de la mort se $pr{\acute{e}}sente$ comme key-world $tr{\grave{e}}s$ important, et cela signifie qu'il parle par la mort une vie $s{\acute{e}}rieuse$ et vraie. Pour Kierkegaard la mort signifie d'abord la mort de la vie mondaine ou la $n{\acute{e}}gation$ de soi, cela est en faveur de sa conception de la nature humaine $o{\grave{u}}$ l'homme est fondamentalement un ${\hat{e}}tre$ $probl{\grave{e}}matique$ et ${\grave{a}}$ la fois ceuli qui a un rapport avec $l^{\prime}{\acute{e}}ternel$. Le $d{\acute{e}}sespoir$ de l'homme sur la vie $pr{\acute{e}}sente$ peut devenir 'la maladie qui entraîne la mort' c'est-${\grave{a}}$-dire la mort spirituelle, mais il peut donner aussi une chemin par laquelle l'homme se dirige en tant qu'individu vers l'Absolu. Chez lui ${\hat{e}}tre$ $s{\acute{e}}rieux$ signifie devenir existentiellement par la $n{\acute{e}}gation$ de soi. Et l'absence de la $sinc{\acute{e}}rit{\acute{e}}$ signifie l'absence de soi en tnat $qu^{\prime}{\hat{e}}tre$ spirituel. Ainsi la $pens{\acute{e}}e$ $s{\acute{e}}rieuse$ sur la mort $n^{\prime}{\acute{e}}tant$ autre chose que de penser la mort comme la partie de $l^{\prime}{\hat{e}}tre$ $pr{\acute{e}}sent$, elle devient la source ${\acute{e}}nergique$ qui permet de vivre pleinement le $pr{\acute{e}}sent$ comme $r{\acute{e}}alit{\acute{e}}$ $li{\acute{e}}$ ${\acute{a}}$ $l^{\prime}{\acute{e}}ternit{\acute{e}}$. Sa $pens{\acute{e}}e$ $s{\acute{e}}rieuse$ sur la mort permet d'avoir une conviction religieuse par laquelle l'homme peut penser la mort corporelle comme aventure $li{\acute{e}}e$ ${\grave{a}}$ $l^{\prime}{\acute{e}}ternit{\acute{e}}$ et par laquelle l'homme peut penser aussi la vie $apr{\grave{e}}s$ la mort comme vraie vie que les justes avaient $d{\acute{e}}sir{\acute{e}}s$. Cette $pens{\acute{e}}e$ de Kierkegaard sur la mort signifie le sens $m{\acute{e}}taphysique$ sur la mort au sens $o{\grave{u}}$ elle est une $r{\acute{e}}alit{\acute{e}}$ $v{\acute{e}}cue$, et aussi la $pens{\acute{e}}e$ qui ${\acute{e}}claircit$ la sagesse des philosophes antiques ${\grave{a}}$ la perspective $chr{\acute{e}}tienne$ qui dit philosopher, c'est apprendre ${\grave{a}}$ mourir.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.30-37
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• 2006

In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.302-310
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• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Journal of the Semiconductor & Display Technology
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• v.7 no.1
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• pp.1-5
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• 2008

In this paper, we fabricated pressure difference type gas flow sensor using only dry etching technology by ICP-RIE(inductive coupled plasma reactive ion etching). The sensor's structure consists of a common shear stress type piezoresistive pressure sensor with an orifice fabricated in the middle of the sensor diaphragm. Generally, structure like diaphragm is fabricated by wet etching technology using TMAH, but we fabricated diaphragm by only dry etching using ICP-RIE. To equalize the thickness of diaphragm we applied insulator($SiO_2$) layer of SOI(Si/$SiO_2$/Si-sub) wafer as delay layer of dry etching. Size of fabricated diaphragm is $1000{\times}1000{\times}7\;{\mu}m^3$ and overall chip $3000{\times}3000{\times}7\;{\mu}m^3$. We measured the variation of output voltage toward the change of gas pressure to analyze characteristics of the fabricated sensor. Sensitivity of fabricated sensor was relatively high as about 1.5mV/V kPa at 1kPa full-scale. Nonlinearity was below 0.5%F.S. Over-pressure range of the fabricated sensor is 100kPa or more.