• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2136-2149
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• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.1
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• pp.67-75
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• 2019

When a Solidity smart contract has a problem in calling a function of another contract, the fallback function is supposed to be executed automatically. However, it may be are arbitrarily created, with their behaviors unknown to developers, and fallback function execution is vulnerable to exploits by attackers. in In this paper, we propose a preprocessing based method to reduce the risk with less overhead of developers'. Developers mark the intention using the newly defined keywords in this paper, and the preprocessor reduces the risk by preprocessing the conditional variables and conditional statements according to the keywords.

• International Journal of Computer Science & Network Security
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• v.22 no.1
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• pp.167-174
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• 2022

In metaheuristic algorithms such as Genetic Algorithm (GA), initial population has a significant impact as it affects the time such algorithm takes to obtain an optimal solution to the given problem. In addition, it may influence the quality of the solution obtained. In the machine learning field, feature selection is an important process to attaining a good performance model; Genetic algorithm has been utilized for this purpose by scientists. However, the characteristics of Genetic algorithm, namely random initial population generation from a vector of feature elements, may influence solution and execution time. In this paper, the use of a statistical algorithm has been introduced (Chi2) for feature relevant checks where p-values of conditional independence were considered. Features with low p-values were discarded and subject relevant subset of features to Genetic Algorithm. This is to gain a level of certainty of the fitness of features randomly selected. An ensembled-based learning model for Hepatitis has been developed for Hepatitis C stage classification. 1385 samples were used using Egyptian-dataset obtained from UCI repository. The comparative evaluation confirms decreased in execution time and an increase in model performance accuracy from 56% to 63%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.29-38
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• 1997

As the trend of the automation is increasing, the usage of the programmable automation equipments like programmable controller(PC), numerical controller(NC), distributed control systems(DCS) and robot controller is greatly expanding in the area of the industrial equipments. But the development of the programing language for the programmable automatic equipment is rarely accomplished. In this paper, we propose design and implementation technique of the real-time mechanism control language by adding time constraint constructs and timing analysis constructs ot conditional statement and iteration statement of a programming language. Moreover, we made it possible to predict plausibility of time constraint constructs of a real time application program at compilation time and developing execution time analysiss technique.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.8
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• pp.309-315
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• 1986

We proposed a preliminary Data Flow Machine Model(DNL1) operating on the basis of Node Label. In this model, all the PMs(Processing Modules) were synchronized with the content of LC(Level Counter) and were not implemented dy the processing cability on conditional nodes. This paper presents an architecture of a concurrent multiprocessor system which was developed from DNL1 with two additional types of memories, CF(Control Flag) and ETF (Enabled Token Flag). The CF memory holds the control condition flag ('1' or '0') to be referenced to when a node is fired and the ETF represents the firability of a certain node. Firable nodes are fetched to the PU(Processing Unit) and processed. This Data Flow system can be extended hierarchically by a network of simple modules. The principle working elements of the machine are a set of PMs, each of which performs the execution of the data flow procedures held in a local memory, NTM(Node Token Memory) within the PM.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.55-64
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• 2017

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2751-2762
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• 1998

In this paper, a new priority assignment ploicy and concurrency control for improvement of transaction predictability and performance are proposed. We present a new priority assignment algorithm called classified priority assignment(CPA), which solves the defects of Earliest Deadline First(EDF) by using class and bucket, and deals with real-time transaction and time-sharing transaction effectively. Also, we present a new concurrency control policy called conditional optimistic concurrency control using lock. It uses optimistic concurrency control for improvement of predictability, and solves transaction conflict by considering priority and execution time of transaction to waste less system resource.

• Communications for Statistical Applications and Methods
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• v.19 no.3
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• pp.459-469
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• 2012

This article proposes a couple of parallel implementations of the self-organizing network for normal mixtures. In principle, self-organizing networks should be able to be implemented in a parallel computing environment without issue. However, the network for normal mixtures has inherent problem in being operated parallel in pure sense due to estimating conditional expectations of the mixing proportion in each iteration. This article shows the result of the parallel implementations of the network using Java. According to the results, both of the implementations achieved a faster execution without any performance degradation.