The Transactions of the Korean Institute of Electrical Engineers (대한전기학회논문지)
- Volume 35 Issue 8
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- Pages.309-315
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- 1986
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- 0254-4172(pISSN)
Implementation of Iteration Loop in DNL1
DNL1 에서 반복류프처리장치의 설계
Abstract
We proposed a preliminary Data Flow Machine Model(DNL1) operating on the basis of Node Label. In this model, all the PMs(Processing Modules) were synchronized with the content of LC(Level Counter) and were not implemented dy the processing cability on conditional nodes. This paper presents an architecture of a concurrent multiprocessor system which was developed from DNL1 with two additional types of memories, CF(Control Flag) and ETF (Enabled Token Flag). The CF memory holds the control condition flag ('1' or '0') to be referenced to when a node is fired and the ETF represents the firability of a certain node. Firable nodes are fetched to the PU(Processing Unit) and processed. This Data Flow system can be extended hierarchically by a network of simple modules. The principle working elements of the machine are a set of PMs, each of which performs the execution of the data flow procedures held in a local memory, NTM(Node Token Memory) within the PM.
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