Browse > Article
http://dx.doi.org/10.5573/ieie.2017.54.6.55

Architecture design for speeding up Multi-Access Memory System(MAMS)  

Ko, Kyung-sik (Department of Information Communications Engineering, ChungNam National University)
Kim, Jae Hee (Department of Information Communications Engineering, ChungNam National University)
Lee, S-Ra-El (Department of Information Communications Engineering, ChungNam National University)
Park, Jong Won (Department of Information Communications Engineering, ChungNam National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.54, no.6, 2017 , pp. 55-64 More about this Journal
Abstract
High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.
Keywords
Architecture Minimize; Parallel Processing; Multi-Access Memory System; Image Processing; SIMD Computer;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 J.H. Kim, K.S. Ko, C.S. Oh, and J.W. Park, "64 Processing Elements with Multiaccess Memory System to Speedup Image Correlation," Advanced Science Letters, Volume 22, Number 9, pp. 2376-2380(5), September 2016.   DOI
2 D. C. Van Voorhis and T. H. Morrin, "Memory systems for image processing," IEEE Trans. Comput., vol. C-27, pp. 113-125, Feb. 1978.   DOI
3 P. Budnik and D. J. Kuck, "The Organization and Use of Parallel Memories," IEEE Trans. Computers, vol.C-20, no. 12, pp. 1566-1569, Dec. 1971.   DOI
4 H. Lee, H. K. Cho, D.S. You and J. W. Park, "An MAMS-PP4: Multi-Access Memory System used to improve the processing speed of visual media applications in a parallel processing system," IEICE Trans. Fundamentals. vol. E87 A, no. 11 November, 2004.
5 J.H. Lim, S. M. Park, J. W. Park, "Design to Chip with Multi-Access Memory System and Parallel Processor for 16 Processing Elements of Image Processing Purpose," Journal of Korea Multimedia Society Vol. 14, No. 11, pp. 1401-1408 November. 2011.   DOI
6 J.S. Park, J.H. Kim, K.S. Ko, J.W. Park, "Feature Extraction System for High-Speed Fingerprint Recognition using the Multi-Access Memory System," Journal of Korea Multimedia Society Vol. 16, No. 8, pp. 914-926, August 2013.   DOI
7 J.W. Park, "An Efficient Memory system for Image Processing," IEEE Trans. Computers, Vol. C-35, No. 7, pp. 669-674, Jul. 1986.   DOI
8 J.W. Park, "Multiaccess Memory System for Attached SIMD Computer," IEEE Trans. on Computers, Vol. 53, No. 3, pp. 1439-452, Apr. 2004.
9 Y-J Lee, J.H. Kim, and J.W. Park, "Performance Analysis of Implementation on Image Processing Algorithm for Multi-Access Memory System Including 16 Processing Elements," Journal of the Institute of Electronics Engineers of Korea, Volume 49, Number 3, pp. 8-14, 2012.