Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Architecture design for speeding up Multi-Access Memory System(MAMS)

Multi-Access Memory System(MAMS)의 속도 향상을 위한 아키텍처 설계

  • Ko, Kyung-sik (Department of Information Communications Engineering, ChungNam National University) ;
  • Kim, Jae Hee (Department of Information Communications Engineering, ChungNam National University) ;
  • Lee, S-Ra-El (Department of Information Communications Engineering, ChungNam National University) ;
  • Park, Jong Won (Department of Information Communications Engineering, ChungNam National University)
  • 고경식 (충남대학교 정보통신공학과) ;
  • 김재희 (충남대학교 정보통신공학과) ;
  • 이스라엘 (충남대학교 정보통신공학과) ;
  • 박종원 (충남대학교 정보통신공학과)
  • Received : 2017.02.15
  • Accepted : 2017.05.24
  • Published : 2017.06.25
Download PDF
⟨ Previous Next ⟩

Abstract

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

대용량 고화질의 영상 응용분야에서는 많은 양의 데이터를 고속으로 처리하는 기술이 필요하며, 이를 위해 고속화된 병렬처리 시스템이 요구된다. 2004년 park은 병렬처리 메모리의 충돌 없이 여러 처리기에 데이터를 접속할 수 있는 방법을 제안하였다. 제안된 MAMS(Multi-Access Memory System) 는 이후 MAMS-PP16 및 MAMS-PP64 등으로 추가적인 연구가 이루어졌다. MAMS는 병렬처리를 위한 메모리 아키텍처로써 One-chip으로 구성되어야하기 때문에 기존 MAMS와 동일한 기능을 수행하면서 아키텍처의 최소화 하는 방법의 연구가 필요하다. 주소 계산 (ACR : Address Calculation and Routing) circuit과 MMS(Memory Module Selection)circuit의 아키텍처는 메모리에 있는 데이터를 병렬처리기(Prossing Elements)들에게 전달한다. 본 논문에서는 MMS circuit을 사용하지 않고 ACR circuit 내부에 1개의 쉬프트와 메모리 모듈의 개수만큼의 조건문으로 구성하는 방법을 통해 아키텍처를 최소화 하는 방법을 제안한다. 구현한 아키텍처의 검증을 위해 Image correlation 실험을 하였다. 실험을 통하여 제안된 MAMS-PP64의 처리시간을 측정 하였으며, 그 결과 Ratio가 평균 1.05향상 된 결과를 확인 할 수 있었다.

Keywords

References

  1. J.W. Park, "An Efficient Memory system for Image Processing," IEEE Trans. Computers, Vol. C-35, No. 7, pp. 669-674, Jul. 1986. https://doi.org/10.1109/TC.1986.1676813
  2. J.W. Park, "Multiaccess Memory System for Attached SIMD Computer," IEEE Trans. on Computers, Vol. 53, No. 3, pp. 1439-452, Apr. 2004.
  3. Y-J Lee, J.H. Kim, and J.W. Park, "Performance Analysis of Implementation on Image Processing Algorithm for Multi-Access Memory System Including 16 Processing Elements," Journal of the Institute of Electronics Engineers of Korea, Volume 49, Number 3, pp. 8-14, 2012.
  4. J.H. Kim, K.S. Ko, C.S. Oh, and J.W. Park, "64 Processing Elements with Multiaccess Memory System to Speedup Image Correlation," Advanced Science Letters, Volume 22, Number 9, pp. 2376-2380(5), September 2016. https://doi.org/10.1166/asl.2016.7820
  5. D. C. Van Voorhis and T. H. Morrin, "Memory systems for image processing," IEEE Trans. Comput., vol. C-27, pp. 113-125, Feb. 1978. https://doi.org/10.1109/TC.1978.1675045
  6. P. Budnik and D. J. Kuck, "The Organization and Use of Parallel Memories," IEEE Trans. Computers, vol.C-20, no. 12, pp. 1566-1569, Dec. 1971. https://doi.org/10.1109/T-C.1971.223171
  7. H. Lee, H. K. Cho, D.S. You and J. W. Park, "An MAMS-PP4: Multi-Access Memory System used to improve the processing speed of visual media applications in a parallel processing system," IEICE Trans. Fundamentals. vol. E87 A, no. 11 November, 2004.
  8. J.H. Lim, S. M. Park, J. W. Park, "Design to Chip with Multi-Access Memory System and Parallel Processor for 16 Processing Elements of Image Processing Purpose," Journal of Korea Multimedia Society Vol. 14, No. 11, pp. 1401-1408 November. 2011. https://doi.org/10.9717/kmms.2011.14.11.1401
  9. J.S. Park, J.H. Kim, K.S. Ko, J.W. Park, "Feature Extraction System for High-Speed Fingerprint Recognition using the Multi-Access Memory System," Journal of Korea Multimedia Society Vol. 16, No. 8, pp. 914-926, August 2013. https://doi.org/10.9717/kmms.2013.16.8.914