• The Mathematical Education
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• v.45 no.1 s.112
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• pp.35-60
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• 2006

In the seventh mathematics curriculum, the use of technological tools including calculator and computer are generally recommended through the seventh subjects related to mathematics emphasized, and especially in 'Applied Mathematics' subject, their use are more strongly emphasized and reflected. The total four kinds of textbooks of Applied Mathematics includes contents on their use. This study investigates what are contents on calculator use, how they are developed and constructed in Applied Mathematics Textbook. Furthermore, this study is focused on the analysis and comparison on those factors of four kinds of textbooks. Based on these results, this study ultimately hope to suggest how effectively calculator use be developed and constructed in textbook both in Applied Mathematics and the other mathematics subjects.

• Journal of Educational Research in Mathematics
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• v.8 no.1
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• pp.251-568
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• 1998

It is the purpose of this study that is to examine the practice and awareness on the use of calculator and to find the method to utilize the calculator as the tool in elementary school mathematics. Recently, it is recommendes strongly to use technical tools such as calculator and computer for the quiltative development on mathematics education. But we prohibite the usage of calculator and do not have the policy to use the calculator in our country because we have little understanding about it. The following direction for educational development is focused not on the repeat learning through the written computation, but on the ability for students to choose an operator and to perform the task with their own objects and strategies. By using the calculator, We can do the followings : 1)to help the mathematical concept develop, 2)to expand the computational ability from written computation to both mental computation and computational estimation, 3)to use the practical value in the problem situation, 4)to reinforce the problem solving, 5)to obtain the interest and the confedence on mathematics. Therefore, we must endevor actively for the broad usage of calculator in the mathematics class.

• Journal of Educational Research in Mathematics
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• v.8 no.1
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• pp.237-249
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• 1998

Calculators can be instructional instruments to be used specially in problem situations which need calculations through calculators. A calculator-calculations is one of the various calculation methods. As there are problem situations for each method, there are problem situations for a calculator-calculation, too. Basically, calculator-calculations can be admitted in any cases which need not paper-and-pencil calculations, estimations, mental calculations, and computer-calculations. In this paper, some basic knowledges on how to use calculators in elementary mathematics education are offered. Students learn concepts easier by doing complex and tedious calculations through calculators than through paper-and-pencil calculations. And, by doing complex and tedious calculations in problem solving, they can focus on understanding problems, planning, and looking back. Calculator can be used directly in phases of understanding and planning. Calculators can be used to practice guess and check strategies. Problems which contain calculations beyond students' paper-and-pencil calculations abilities. So, as a result, students' experiences on problem solving can be extended. Calculators experiences can affect students' persistences, confidences, enthusiasms, self-esteems positively.

• The Journal of Korean Association of Computer Education
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• v.8 no.2
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• pp.33-40
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• 2005

It has been found that the learning method based on conventional CAI(Computer Assisted Instruction) to be inadequate and inefficient as it is designed without considering the individual learning characteristics of the learners. In order to rectify and remedy the problem, the development of an ITS(Intelligent Tutoring System) that is adequately equipped with an artificial intelligence that successfully interprets the individual learning ability characteristics through accumulated individual data is in order. This study attempts to verify the individual acquisition ability and the possible error committed by learners in the process of learning in order to present the elements to be considered for designing a successful student module that enables the effective learning through the 'learner ability grouping' for learning Electronic Calculator Architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.279-282
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• 2012

In this paper, a hardware architecture of phase calculator for 3D image processing is proposed. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. Phase calculator designed in Verilog HDL is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.54-63
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• 2011

This paper proposes a new equation to calculate computer-generated hologram (CGH) in a high speed and its cell-based VLSI (veri large scale integrated circuit) architecture. After finding the calculational regularity in the horizontal or vertical direction from the basic CGH equation, we induce the new equation to calculate the horizontal or vertical hologram pixel values in parallel. We also propose the architecture of the CGH cell consisting of a initial parameter calculator and update-phase calculator(s) on the basis of the equation and implement them in hardware. Also we show a hardware architecture to parallelize the calculation in the horizontal direction by extending CGH. In the experiments we analyze the used hardware resources. These analyses makes it possible to select the amount of hardware to the precision of the results. Here, for the CGH kernel and the structure of the processor, we used the platform from our previous works.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.263-264
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of 0.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation or in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA implementation results for the proposed structure show 39% and 32% gate count reduction comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.