• 제목/요약/키워드: complementary metal-oxide-semiconductor

검색결과 195건 처리시간 0.02초

새로운 $TiSi_2$ 형성방법과 STI를 이용한 초박막 게이트 산화막의 특성 개선 연구 (Study of Improvement of Gate Oxide Quality by Using an Advanced, $TiSi_2$ process & STI)

  • 엄금용;오환술
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.41-44
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    • 2000
  • Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

  • Baek, Ki-Ju;Na, Kee-Yeol;Park, Jeong-Hyeon;Kim, Yeong-Seuk
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권5호
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    • pp.522-529
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    • 2013
  • In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

CMOS 이미지 센서의 CDS

  • 백남대
    • 광학세계
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    • 통권90호
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    • pp.60-65
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    • 2004
  • 현대의 정보통신 사회에 있어서 카메라는 여러 분야에 사용이 되고 있다. 카메라는 아날로그사진에서 피사체를 기록하기위한 필름을 사용하는데 이미지 센서는 빛을 변환하는 역할을 하는 필름대용품으로 사용되는 것이다. 이 이미지 센서는 전하결합소자(CCD : Charge Coupled Device)와 상보금속 산화물반도체(CMOS : Complementary Metal-Oxide-Semiconductor)가 대표적이다. 특히 디지털 카메라를 이용하여 과거의 카메

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비정질 및 단결정 실리콘에서 10~50 keV 에너지로 주입된 안티몬 이온의 분포와 열적인 거동에 따른 연구 (A Study on Implanted and Annealed Antimony Profiles in Amorphous and Single Crystalline Silicon Using 10~50 keV Energy Bombardment)

  • 정원채
    • 한국전기전자재료학회논문지
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    • 제28권11호
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    • pp.683-689
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    • 2015
  • For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

  • Kim, Yong-Bin
    • Transactions on Electrical and Electronic Materials
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    • 제12권5호
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    • pp.175-188
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    • 2011
  • As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

확장성을 고려한 QCA XOR 게이트 설계 (Design of Extendable XOR Gate Using Quantum-Dot Cellular Automata)

  • 유영원;김기원;전준철
    • 한국항행학회논문지
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    • 제20권6호
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    • pp.631-637
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    • 2016
  • CMOS (complementary metal-oxide-semiconductor)의 소형화에 대한 한계를 극복할 수 있는 대체 기술 중 하나인 양자 셀룰라 오토마타 (QCA; quantum cellular automata)는 나노 단위의 셀들로 이루어져 있고, 전력의 소모량이 매우 적은 것이 특징이다. QCA를 이용한 다양한 회로들이 연구되고 있고, 그 중에서 XOR (exclusive-OR)게이트는 오류 검사 및 복구에 유용하게 사용되고 있다. 기존의 XOR 논리 게이트는 확장성이 부족하고, 클럭 구간의 수가 많이 소요되며, 실제 구현에 어려움이 있는 경우가 많다. 이러한 단점을 극복하기 위해 클럭 구간의 수를 단축한 다수결 게이트를 이용한 XOR 논리 게이트를 제안한다. 제안한 회로는 기존의 XOR 논리 게이트들과 비교 분석하고 그 성능을 검증한다.

A dual-path high linear amplifier for carrier aggregation

  • Kang, Dong-Woo;Choi, Jang-Hong
    • ETRI Journal
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    • 제42권5호
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    • pp.773-780
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    • 2020
  • A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

차세대 웨어러블 전자시스템용 실리콘 나노선 트랜지스터 연구 (Research on Silicon Nanowire Transistors for Future Wearable Electronic Systems)

  • 임경민;김민석;김윤중;임두혁;김상식
    • 진공이야기
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    • 제3권3호
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    • pp.15-18
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    • 2016
  • In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

Development of a multi-modal imaging system for single-gamma and fluorescence fusion images

  • Young Been Han;Seong Jong Hong;Ho-Young Lee;Seong Hyun Song
    • Nuclear Engineering and Technology
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    • 제55권10호
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    • pp.3844-3853
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    • 2023
  • Although radiation and chemotherapy methods for cancer therapy have advanced significantly, surgical resection is still recommended for most cancers. Therefore, intraoperative imaging studies have emerged as a surgical tool for identifying tumor margins. Intraoperative imaging has been examined using conventional imaging devices, such as optical near-infrared probes, gamma probes, and ultrasound devices. However, each modality has its limitations, such as depth penetration and spatial resolution. To overcome these limitations, hybrid imaging modalities and tracer studies are being developed. In a previous study, a multi-modal laparoscope with silicon photo-multiplier (SiPM)-based gamma detection acquired a 1 s interval gamma image. However, improvements in the near-infrared fluorophore (NIRF) signal intensity and gamma image central defects are needed to further evaluate the usefulness of multi-modal systems. In this study, an attempt was made to change the NIRF image acquisition method and the SiPM-based gamma detector to improve the source detection ability and reduce the image acquisition time. The performance of the multi-modal system using a complementary metal oxide semiconductor and modified SiPM gamma detector was evaluated in a phantom test. In future studies, a multi-modal system will be further optimized for pilot preclinical studies.

전송 게이트가 내장된 Gate/Body-Tied P-Channel Metal-Oxide Semiconductor Field-Effect Transistor 구조 광 검출기를 이용한 감도 가변형 능동 화소 센서 (Adjusting the Sensitivity of an Active Pixel Sensor Using a Gate/Body-Tied P-Channel Metal-Oxide Semiconductor Field-Effect Transistor-Type Photodetector With a Transfer Gate)

  • 장준영;이제원;권현우;서상호;최평;신장규
    • 센서학회지
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    • 제30권2호
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    • pp.114-118
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    • 2021
  • In this study, the sensitivity of an active pixel sensor (APS) was adjusted by employing a gate/body-tied (GBT) p-channel metal-oxide semiconductor field-effect transistor (PMOSFET)-type photodetector with a transfer gate. A GBT PMOSFET-type photodetector can amplify the photocurrent generated by light. Consequently, APSs that incorporate GBT PMOSFET-type photodetectors are more sensitive than those APSs that are based on p-n junctions. In this study, a transfer gate was added to the conventional GBT PMOSFET-type photodetector. Such a photodetector can adjust the sensitivity of the APS by controlling the amount of charge transmitted from the drain to the floating diffusion node according to the voltage of the transfer gate. The results obtained from conducted simulations and measurements corroborate that, the sensitivity of an APS, which incorporates a GBT PMOSFET-type photodetector with a built-in transfer gate, can be adjusted according to the voltage of the transfer gate. Furthermore, the chip was fabricated by employing the standard 0.35 ㎛ complementary metal-oxide semiconductor (CMOS) technology, and the variable sensitivity of the APS was thereby experimentally verified.