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http://dx.doi.org/10.5573/JSTS.2013.13.5.522

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET  

Baek, Ki-Ju (Dept. of Semiconductor Eng., Chungbuk National University)
Na, Kee-Yeol (Dept. of Semiconductor Electronics, Chungbuk Provincial College)
Park, Jeong-Hyeon (DSD Division, Magnachip Semiconductor)
Kim, Yeong-Seuk (Dept. of Semiconductor Eng., Chungbuk National University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.13, no.5, 2013 , pp. 522-529 More about this Journal
Abstract
In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.
Keywords
shallow trench isolation (STI); subthreshold hump effect; high-voltage; MOSFET; work function; layout; narrow width effect (NWE); inverse narrow width effect (INWE);
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