• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2055-2057
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• 2004

The Ku band that has been using for the satellite communication and broadcasting would be changed to K/Ka bands. The satellite system requires the antenna structure to fabricate low loss and small antenna that is able to be integrated with other Rf circuits for both Rx and Tx. So we should design it with dual feed antennas at K/Ka bands, high isolation between two different feeds and broadband circular polarization. This paper proposes the LTCC(Low Temperature Co-fired Ceramic) process for integration with other Rf circuits and the Axial mode of the helical antenna to satisfy those requirements.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.395-398
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gun control were proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0mA to 300mA over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than $1.4\%$ over the current range from 0A to 300mA.

• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• ETRI Journal
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• v.30 no.5
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• pp.729-734
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• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.9
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• pp.481-487
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• 2004

The Ku band that has been using for the satellite communication and broadcasting would be changed to K/Ka bands. The satellite system requires the antenna structure to fabricate low loss and small antenna that is able to be integrated with other Rf circuits for both Rx and Tx. So we should design it with dual feed antennas at K/Ka bands, high isolation between two different feeds and broadband circular polarization. This paper proposes the LTCC(Low Temperature Co-fired Ceramic) process for integration with other Rf circuits and the Axial mode of the helical antenna to satisfy those requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2033-2042
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• 1996

In this papre, we describe a recently implemented echo canceller for digital cellular communication of Code Division Multiple Access(CDMA) that features time sharing of digital signal processor(DSP) over four channels in one DSP to reduce per channel costs. In the Public Land Mobile Network(PLMN), it is important to cancel the echo reflected from the Public Switched Telephone Network(PSTN) side. In case of digital mobile system, the round-trip delay of the echo is in excess of about 180 milliseconds due to frame-by-frame voice coding. It is necessary to cancel the echo in PLMN. We have developed a multi-channel echo canceller tht operates with Time Switch Module in a Mobile Switching Center(MSC). The general echo canceller needs PCM trunk interface circuits and the tone detection and disabling circuits, but the multi-channel echo canceller linked with Time Switch Module does not need them. Therefore we could develop the effective and economical echo canceller.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.391-394
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• 2000

In this paper four lossy and one lossless inductance simulator topologies employing a single DO-OTA are presented. For the topologies proposed the inductance $L_{eq}$ and the series resistance $R_{eq}$ are independently adjustable. The topologies employ a single capacitor and are canonic in the number of capacitors. The resistors in the topologies can easily be implemented also with DO-OTAs. In this case the topologies proposed change to DO-OTA-C inductor simulators which is important from the integration point of view. Simulation results are included to verify theory.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.123-126
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• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.882-885
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• 2011

This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.