• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.397-403
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• 2015

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

• International Journal of Advanced Culture Technology
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• 제7권4호
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• pp.96-103
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• 2019

In this paper, we propose two-stage multichannel architecture for oyster product management system, called cloud stage and agent stage. There are two communication channels at each stage. In cloud stage, the embedded system in the smart scale communicates with the server through two channels, Ethernet or 3G/LTE mobile communication. In agent stage, PCs and smart phones called agents communicate with the server also through Internet and 3G/LTE mobile communication. Compared with previous system in which the amount of the oyster produced in oyster workplaces could be monitored only at the console of only one oyster main server, developed system makes it possible to monitor the amount of produced oyster at several PCs (or smart phones). In addition to the amount of oysters produced at all oyster workplaces the environment of oyster workplaces such as temperature and humidity can be monitored on agents to judge the freshness. Two-stage architecture with multiple channels makes it possible to monitor the amount of oyster product and environment of the oyster workplace at any place in real time.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 한국통신학회논문지
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• 제34권10C호
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• pp.946-954
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• 2009

일반적인 RFID 시스템에서는 리더와 백 엔드 데이터베이스 사이의 통신 채널을 안전한 채널로 가정하고 있다. 하지만 응용 환경에 따라 리더와 데이터베이스 사이의 통신 채널이 리더와 태그 간의 통신 채널처럼 안전하지 않은 채널을 통하여 메시지를 송수신 하게 되는 경우가 얼마든지 존재한다. 본 논문에서는 데이터베이스, 리더 그리고 태그 간의 모든 통신 채널이 안전하지 않은 공개 채널임을 가정하여 공개 채널 기반의 안전한 RFID 상호인증 프로토콜을 제안한다. 제안한 프로토콜은 공개된 채널 상에 송수신되는 모든 통신 메시지의 인증과 무결성을 보장하기 위해 안전한 일방향 해쉬 함수를 사용하였다. 또한 상호인증 후 데이터베이스와 태그가 다음 세션을 위해 기존의 비밀키를 새로운 비밀키로 각각 갱신하도록 하여 전방향 안전성을 제공하도록 설계하였다.

• 한국정보통신학회논문지
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• 제15권2호
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• pp.299-306
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• 2011

다음은 이 논문에서는 임펄스 잡음과 함께 다중경로 특성을 가진 수중 통신 채널에 대해, 확률거리 최소화와 델타함수열을 이용한 블라인드 적응등화 알고리듬을 소개하고 임펄스 잡음에 대한 강인성을 입증하였다. 기존의 자승평균오차 기반의 CMA는 임펄스 잡음 환경에서 다중경로 채널을 보상하지 못하는 현상을 보였고 엔트로피에 기반을 둔 코렌트로피 등화알고리듬도 일반적 변조방식에서 성능이 만족스럽지 못한 것으로 나타났으나, 델타함수열을 이용한 확률분포 거리최소화 방법은 이러한 임펄스 잡음 문제와 다중경로 채널 블라인드 등화문제를 동시에 해결함을 보였고, 임펄스 잡음에 대해 탁월한 강인성을 가짐을 이론적 분석과 함께 시뮬레이션 실험을 통해 입증하였다.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 1996년도 추계학술대회발표논문집; 고려대학교, 서울; 26 Oct. 1996
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• pp.78-88
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• 1996

It is important to understand the process of IT diffusion between organizations for meeting effectively IT progress and its changes. The previous studies provide, the process of IT diffusion between organizational members, organizational factors facilitating the assimilation of IT within the organization, and the organizational members' usage of communication channels in the IT adoption process. But they failed to provide comprehensively the diffusion process of IT between organizations. Therefore, an empirical research through a field survey has been performed to examine the diffusion process of RDB with 64 companies to overcome the limits of the previous studies. The purpose of this study is (1) to empirically examine the interaction of companies(prior adopters and potential adopters), (2) to look into the differences of the factors of organizational structure and the periods of RDB adoption process between OAE(Organizations Adopting Earlier) and OAL(Organizations Adopting Later), and the importance of communication channels used in IT planning stage and adoption stage, (3) to inquire into the difference of RDB performance between OAE and OAL. The results of this study indicate that there is no interaction between the prior adopters and the potential adopters. Also, there are great significant differences with regards to variables of CEO's age, CEO's concern on IT, formalization, centralization compensation systems, CIO's attitudes on changes, RDB adoption periods, performance of RDB. In addition, interpersonal channels have been much more used than mass communication channels in both IT planning stage and adoption stage. This study provides good guidelines to the companies and the vendors in shaping the strategies of IT adoption and IT diffusion respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2499-2501
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• 2001

Today many researches are accomplished for power line communication. But It is very dangerous to communicate with devices using power line. Because power line is an candidate to cope with the existing communication channels. So It is need to be measured the properties of power line as communication channels, before successful communication system is possible. In this paper, we re-analysis the characteristics of power line and suggest an implementation technique for the high-data-rate power line communication modem.

• Asian Journal for Public Opinion Research
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• 제9권3호
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• pp.293-306
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• 2021

The news and views of Pakistani television channels are extensively shared on digital media for information or analysis where the general public discusses overt and covert agendas by mentioning their factual and presentational style. This study contributes to the contemporary studies of media perception through focus group interviews with 72 randomly selected master's and bachelor's students studying Media and Communication at the School of Media and Communication Studies, University of Management and Technology, Lahore, Pakistan to provide information about the feelings and observations of future journalists and media literates. In summary, the findings of our research exposed the negative perception of Pakistani electronic media among the participants due to what they perceived as biased, inaccurate, and unethical reporting.

• 전기학회논문지P
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• 제63권2호
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• pp.81-88
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• 2014

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.