Browse > Article

The Design of Multi-channel Synchronous and Asynchronous Communication IC for the Smart Grid  

Ock, Seung-Kyu (Electronics Engineering of Cheongju University)
Yang, Oh (School of Electronics and Information Engineering, Cheongju University)
Publication Information
Journal of the Semiconductor & Display Technology / v.10, no.4, 2011 , pp. 7-13 More about this Journal
Abstract
In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.
Keywords
Smart Grid; VHDL; Synchronous communication; Asynchronous communication; CRC-ITU-T;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 Altera Corporation, "Quartus II Web Edition" Available http://www.altera.com/
2 In-Sik Hong, "Design of a 16 bit Basic Computer Processor using VHDL" Soonchunhyang J. Instit, Indust., Technol., 3, pp.615-628, 1997.
3 Doo-Youl Park, "A study on the Modeling and design of Parwan CPU using a VHDL", 한국 OA학회 논문지, 제7권 제2호, pp.20-29, 2002.6.
4 Hee-Don Seo, Moon-Su Kim, Jae-Hoon Kie, Dong-Jin Shin, Young-Tak Kim, "Design of AAL-2 Multimedia Communication Protocol Function Using VHDL", 정보통신연구소 논문집 6권 1호, pp. 47-53, 1999.
5 양 오, "FPGA를 이용한 시퀀스 로직 제어용 고속 프로세서 설계", 대한전기학회 논문지 48권 12호, pp.1554-1563, 1999.
6 ZILOG, "Z80C30/Z85C30 CMOS SCC Serial Communications Controller Product Specification", 2002.
7 옥승규.양 오, "FPGA를 이용한 다채널 비동기 통신용 IC 설계", 전자공학회논문지, 제47권 제1호, pp.28-37, 2010. 1.
8 ATMEL, "8-bit AVR Microcontroller ATmega128 Data Sheet", 2007.
9 Waterman, Steve, "Lab Manual for Digital Electronics with VHDL Quartus Version", 2005.
10 양 오, "논리회로도와 VHDL를 이용한 디지털 시스템 설계", 내하출판사, 2011.
11 이상덕, "Embedded PCI Local Bus Core의 VHDL을 이용한 설계", 석사학위논문, 2003.
12 Sudhakar Yalamanchili, VHDL Starter's Guide, PRENTICE HALL, 1998.
13 이일우, 이정인, "스마트그리드 정보통신기술", 한국통신학회지, 제27권 제11호, pp.1-3, 2010.10.