• 한국통신학회논문지
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• 제33권5C호
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• pp.378-385
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• 2008

본 논문은 고속 임베디드 시스템에 사용하기 위해 CMOS AD 변환기(Analog-to-Digital Converter)를 설계하였다. 이 AD 변환기는 효율적인 구조로 설계하기 위하여 전압을 예측할 수 있는 플래시 AD 변환기와 자동 영을 기반으로 하여 설계된 비교기를 사용하였다. 이 구조의 변환속도는 기존의 플래시 AD 변환기와 거의 같지만 비교기와 연결된 회로가 줄어들었기 때문에 전체 회로의 크기를 크게 줄일 수 있었다. 이 ADC는 $0.25{\mu}m$ 디지털 CMOS 기술로 구현되었다.

• 한국초전도ㆍ저온공학회논문지
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• 제8권1호
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• 한국산업융합학회 논문집
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• 제5권1호
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1037-1040
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• 1998

In this paper, current conveyor building block is introduced and CMOS realization of this block is given. The input-impedance characteristics, current-transfer characteristics and voltage-transfer characteristics of this proposed current conveyor circuit are given. This characteristics of the CMOS current conveyor circuit is useful of the various applications which require a wideband. Using the Spice tool, the circuit is designed and the characteristics of CMOS current conveyor circuit is considered. Finally, refer to the simple applications.

• 방송과미디어
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• 제5권1호
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• pp.59-71
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• 2000

This paper presents a survey of the CMOs-based image sensor and its applications to various real field digital camera. CMOS image sensor, called active pixel sensor (APS), has many interesting properties such ash I회 sensitivity, high speed readout, random access and lower power consumption when it is compared with CCd. this paper also addresses the state-of-the-art of CMOS image sensor, and gives some examples of its application to digital camera and special-purpose cameras. with the advancement of semiconductor technology, CMOS image sensor is a future technology for imaging system, and will be widely used in the filed of image capturing for consumer electronics and scientific measurements.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.103-106
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• 2005

This paper reports design and fabrication of CMOS temperature sensor circuit using MOSIS 0.25um CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. This circuit may be applicable to the design of one-chip IC where quartz crystal resonator is directly mounted on CMOS oscillator chips.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1516-1520
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• 1987

This paper proposes fault simulation algorithms for Domino CMOS circuits, The inputs having fanouts are described correctly in the algorithms by modeling the functional block in the Domino CMOS circuits as Modified dependency matrix. The proposed algorithms generate easily the test sequence which can detect the s-a-O, s-a-I, stuckopen faults in the Domino CMOS circuits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(3)
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• pp.5-8
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• 2000

Voltage mode chaotic neuron has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated CMOS chaotic neuron consist of chaotic signal generator and sigmoid output function. This paper presents an analysis of the chaotic behavior in the voltage mode CMOS chaotic neuron. From empirical equations of the chaotic neuron, the dynamical responses such as time series, bifurcation, and average firing rate are calculated. And, results of experiments in the single chaotic neuron and chaotic neural networks by two neurons are shown and compared with the simulated results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.253-256
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• 2002

A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.