• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• Publications of The Korean Astronomical Society
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• v.28 no.2
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• pp.17-23
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• 2013

Song I-Yeong (1619 ~ 1692), who was an astronomy professor of Gwansanggam (觀象監, Bureau of Astronomy), created the Honcheonsigye (渾天時計, Armillary Clock) in 1669 (10th year of King Hyeonjong Era). Honcheonsigye was a unique astronomical clock which combined an armillary sphere, the traditional astronomical instrument of the Far East, with the power mechanism of western alarm clock. The clock part of this armillary clock is composed of two major parts which are the going-train, power unit used the weight, and the time signal system in a wooden case. The time signal system is composed of four parts which are the time-annunciator, the striking train, the 12 different time-announcing medallions and the sound bell. This clock has been neglected for many years and its several components have been lost. This study is to understand the structure of time signal system and suggests the restoration process.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.17-22
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• 2005

It is important that we maintain the synchronous time-information with each other in the synchronous system. The most functions in the synchronous system need the time-information. n we have the wrong time-information, the system would operate incorrectly. So, we need to check if the time-information is correct or not in the important block of the synchronous system. In this paper, we will discuss how to check the clock signal and find some problem of it. Then, we will suggest the alternative plan.

• ETRI Journal
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• v.30 no.3
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• pp.461-468
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• 2008

This paper presents a chromatic dispersion monitoring technique using a clock-frequency component for carrier-suppressed return-to-zero (CSRZ) signal. The clock-frequency component is extracted by a clock-extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high-speed optical communication systems.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1343-1349
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• 2013

In optical fiber communications, several newly-developed signal formats are used to obtain the best performance within limited spectral bandwidth. CSRZ (carrier-suppressed return-to-zero) format is one of the new signal formats, which has better spectral efficiency and better robustness to dispersion than RZ (return-to-zero) format. Thus it is widely used for demonstrating high-speed optical communication systems. In an earlier research, we proposed a clock-extraction method of CSRZ signal to monitor chromatic dispersion. However, the clock-frequency component extracted by the clock-extraction method can be affected by the bandwidth of a transmitter or a receiver. Therefore, in this paper, we investigate the effect of bandwidth on the chromatic dispersion monitoring of CSRZ signal based on clock-frequency component. As a result, we propose a couple of robust clock-extraction methods to monitor chromatic dispersion in CSRZ signal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.134-139
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• 2004

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of pre-amplifiers, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.