Design of the Clock Recovery Circuit for a 40 Gb/s Optical Receiver
![]() |
박찬호
(경북대학교 전자공학과)
우동식 (경북대학교 전자공학과) 김강욱 (경북대학교 전자공학과) |
1 |
Clock Recovery At Gigabit-persecond Data rates
/
|
2 |
Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop
/
과학기술학회마을 |
3 |
Design considerations and performance requirements for high speed driver amplifiers
/
|
![]() |