• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.708-712
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• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.825-828
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• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.

• ETRI Journal
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• v.27 no.2
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• pp.195-205
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• 2005

In this paper, an error-free Butcher algorithm is introduced to study the singular system of a linear electrical circuit for time invariant and time varying cases. The discrete solutions obtained using Runge-Kutta (RK)-Butcher algorithms are compared with the exact solutions of the electrical circuit problem and are found to be very accurate. Stability regions for the single term Walsh series (STWS) method and the RK-Butcher algorithm are presented. Error graphs for inductor currents and capacitor voltages are presented in a graphical form to show the efficiency of the RK-Butcher algorithm. This RK-Butcher algorithm can be easily implemented in a digital computer for any singular system of electrical circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.43-46
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• 2011

A novel circuit structure of dual-band bandstop filters is proposed in this paper. This structure comprises two shunt-connected tri-section stepped impedance resonators with a transmission line in between. Theoretical analysis from the equivalent circuit and design procedures are described. We represented graphs for filter design from the derived synthesis equations by resonance condition of circuits. Notably, advantages of the proposed filter structure are compact size in design, wide range of realizable resonance frequency ratio, and more realizable impedances.

• Smart Structures and Systems
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• v.17 no.2
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• pp.327-345
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• 2016

The existence of SH-wave in a piezomagnetic layer overlying an initially stressed orthotropic half-space is investigated. The coupled of differential equations are solved for piezomagnetic layer overlying an orthotropic elastic half-space. The general dispersion equation has been derived for both magnetically open circuit and magnetically closed circuits under the four types of boundary conditions. In the absence of the piezomagnetic properties, initial stress and orthotropic properties of the medium, the dispersion equations reduce to classical Love equation. The SH-wave velocity has been calculated numerically for both magnetically open circuit and closed circuits. The effect of initial stress and magnetic permeability are illustrated by graphs in both the cases. The velocity of SH-wave decreases with the increment of wave number.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.11
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• pp.952-957
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• 2003

We propose how to translate relay circuits to the EMFGs(Extended Mark Flow Graphs) formally and analyze the original one by using the mark flow of it. Firstly, the concepts of the output condition, the output-on condition and the output-off condition are introduced in the relay circuits. These can be used to find the structure and the operation of respective relay outputs but the sequential operations of them cannot be obtained from these. Secondly, a relay circuit is translated to the corresponding EMFG as the all output-on conditions and all output-off conditions of it are translated to EMFGs. For the adequate translation, the condition arc and the concepts of the generation transition and the degeneration transition are introduced, and the duality for the simplification of the result. Thirdly, we analyze the operation of the original circuit by analyzing the mark flow of the resulting EMFG. We can achieve easy and fast analysis based on the EMFG's operation algorithm. Finally, we apply these to the relay circuit for an electric furnace and analyze its operation with the mark flow of the resulting EMFG. The formal translation from relay circuits to EMFGs makes the analysis easy so that these results can be used to design, modelling, the fault detection and the maintenance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1653-1658
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• 2011

A novel circuit structure of dual-band bandstop filters is proposed in this paper. This structure comprises two shunt-connected tri-section stepped impedance resonators with a transmission line in between. Theoretical analysis from the equivalent circuit and design procedures are described. We represented graphs for filter design from the derived synthesis equations by resonance condition of circuits. Notably, advantages of the proposed filter structure are compact size in design, wide range of realizable resonance frequency ratio, and more realizable impedances.