The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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Synthesis of Asynchronous Circuits from Free-Choice Signal Transition Graphs with Timing Constraints

시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로의 합성

  • 정성태 (원광대학교 컴퓨터 및 정보통신공학부) ;
  • 정석태 (원광대학교 컴퓨터 및 정보통신공학부)
  • Published : 2002.03.01
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Abstract

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

본 논문에서는 시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로를 합성하는 방법을 기술한다. 이 방법에서는 상태 그래프를 생성하지 않고 신호 전이 그래프로부터 직접 신호 전이들간의 관계를 구하여 비동기 회로를 합성한다. 본 논문의 합성 방법에서는 자유 선택 신호 전이 그래프를 선택 행위가 없는 결정성 신호 전이 그래프에 대하여 타이밍 분석을 수행하여 임의의 두 신호 전이 사이의 시간 제약 병렬 관계와 시간 제약 인과 관계를 구한다. 다음에는 이 관계들을 이용하여 각 결정성 신호 전이 그래프에 대한 합성을 수행하고 그 결과를 합병함으로써 전체 회로를 합성한다. 실험 결과에 의하면 본 논문에서 제안한 합성 방법은 상태 공간이 큰 회로에 대하여 현저하게 합성시간을 단축시킬 수 있을 뿐 만 아니라 기존의 상태 그래프 기반 합성 방법과 비교하여 거의 같은 면적의 회로를 합성한다.

Keywords

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