• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• ETRI Journal
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• v.35 no.5
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

• ETRI Journal
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• v.30 no.1
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• pp.129-140
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• 2008

In this paper, we propose a novel ant colony optimization (ACO)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test-access-mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.3
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• pp.195-199
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• 2014

Various M2M applications have different quality-of-service(QoS) requirements to be implemented practically. QoS requirements are normally data rate and delay constraint. However, there are limited number of wireless communication chip solutions which cannot support QoS requirements for all M2M application. Hence, aggregated usage of plural wireless communication chip solutions should be needed to implement M2M applications. In this paper, we consider the case that two wireless communication chips using random access protocol work together to transmit data of an M2M application. In such case, data rate and delay performance are mathematically analyzed. In our results, practical data rate can be improved from 2.5 to 7 times while delay constraints are satisfied if we simply use two wireless communication chips together.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• Journal of the Korea Society of Computer and Information
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• v.21 no.1
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• pp.39-47
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• 2016

In this paper, we propose vehicle SoC fault diagnosis platform using FlexRay protocol in order to detect the faults of semiconductor control chip even after vehicle production. Before FlexRay protocol by sending NFI (Null Frame Indicator) bit among the header segment and a specific identifier in the payload segment of FlexRay frame, this technique can be distinguishable from normal mode and test mode. By using this technique, it is possible to detect the faults such as performance degradation of vehicle network system caused by the aging or several problems of vehicle semiconductor chip. Also high reliability and safety of vehicle can be maintained by using structural test for vehicle SoC fault detection.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.76-79
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• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.144-149
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• 2013

In this research, we developed a biosensor to detect lung cancer-specific biomarker using Anodic Aluminum Oxide (AAO) chip based on interference and nano surface plasmon resonance (nanoSPR). The nano-porous AAO chip was fabricated $2{\mu}m$ of pore-depth by two-step anodizing method for surface uniformity. NanoSPR has sensitivity to the refractive index (RI) of the surrounding medium and also provides simple and label-free detection when specific antibodies are immobilized to the Au-deposited surface of nano-porous AAO chip. To detect the lung cancer-specific biomarker, antibodies were immobilized on the surface of the chip by Self Assembled Monolayer (SAM) method. Since then lung cancer-specific biomarker was applied atop the antibodies immobilized layer. The specific reaction of the antigen-antibody contributed to the change in the refractive index that cause shift of resonance spectrum in the interference pattern. The Limit of Detection (LOD) was 1 fg/ml by using our nano-porous AAO biosensor chip.