• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.107-108
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• 2007

In order to investigate the electrical properties of Hf-silicate as a function of annealing temperature, Hf-silicate deposited by atomic layer deposition (ALD) was studied. After Hf-silicate film deposition, annealing was proceeded at $500^{\circ}C\;and\;700^{\circ}C$. The hysteresis of C-V curves and trapping charge densities were decreased after annealing process. As annealing temperature became higher from $500^{\circ}C\;to\;700^{\circ}C$, the capacitance equivalent thickness (CET) was increased from 1.66 nm to 1.76 nm and the leakage current at -1 V was decreased from $1.70{\times}10^{-4}\;to\;5.68{\times}10^{-5}\;A/cm^2$.

• Bulletin of the Korean Chemical Society
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• 제14권6호
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• pp.740-743
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• 1993

By considering both electron-electron and electron-lattice interactions, the effect of charge transfer on the bond structure and electronic states of $C_{60}$ is studied without configuration limitation. The results show that the electron-electron interaction does not eliminate the layer structure of the bond distortion and the self-trapping of transferred electrons. For charged ${C_{60}}^{2-}$, there exist two localized electronic states, which possess laminar wave functions, and four nonequivalent groups of carbon atoms, which induce a fine-structure in the NMR spectrum line.

• 반도체디스플레이기술학회지
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• 제23권2호
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• pp.60-64
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• 2024

The threshold voltage shift in thin-film transistors (TFTs) is modeled using stretched-exponential (SE) and stretched-hyperbola (SH) functions. These models are derived by introducing empirical parameters into reaction rate equations that describe defect generation or charge trapping caused by hydrogen diffusion in the dielectric or interface. Separately, the dielectric relaxation phenomena are also described by the same reaction rate equations based on defect diffusion. Dielectric relaxation was initially modeled using the SE model, and various models have been proposed using fractional calculus. In this study, the characteristics of the threshold voltage shift and the dielectric relaxation phenomena are compared and analyzed to explore the applicability of analytical models used in the field of dielectric relaxation, in addition to the conventional SE and SH models.

• 대한전자공학회논문지SD
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• 제41권7호
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• pp.21-29
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• 2004

본 논문에서는 Dual oxide를 갖는 Nano-scale CMOSFET에서 각 소자의 Hot carrier 특성을 분석하여 두 가지 중요한 결과를 나타내었다. 하나는 NMOSFET Thin/Thick인 경우 CHC stress 보다는 DAHC stress에 의한 소자 열화가 지배적이고, Hot electron이 중요하게 영향을 미치고 있는 반면에, PMOSFET에서는 특히 Hot hole에 의한 영향이 주로 나타나고 있다는 것이다. 다른 하나는, Thick MOSFET인 경우 여전히 NMOSFET의 수명이 PMOSFET의 수명에 비해 작지만, Thin MOSFET에서는 오히려 PMOSFET의 수명이 NMOSFET보다 작다는 것이다. 이러한 분석결과는 Charge pumping current 측정을 통해 간접적으로 확인하였다. 따라서 Nano-scale CMOSFET에서의 NMOSFET보다는 PMOSFET에 대한 Hot camel lifetime 감소에 관심을 기울여야 하며, Hot hole에 대한 연구가 진행되어야 한다고 할 수 있다.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.156-160
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• 2006

Al2O3 층의 유무에 따른 Ge 나노입자가 형성된 MOS 구조의 캐패시터의 전압에 대한 캐패시턴스 (C-V)의 특성을 측정하였다. Al20O층이 형성된 MOS 캐패시터의 C-V 곡선은 전압의 변화에 대해 나타나는 반시계 방항의 히스테리시스 특성은 Si 기판과 Ge 나노입자 사이를 전자가 터널링하여 Ge 나노입자에 저장되었기 때문이다. Al2O3 층이 없는 MOS 캐패시터의 경우, 시계 방향의 히스테리시스 특성과 좌측으로 이동한 플랫-밴드 전압 값을 볼 수 있다. 이것은 SiO2 층에 존재하는 산소 결원 (oxygen vacancy) 으로 인한 전하 트랩이 이러한 특성을 나타냈다 할 수 있다. 또, 백색광이 C-V 특성에 미치는 영향에 대하여 논하였다.

• 한국재료학회지
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• 제1권3호
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• pp.125-131
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• 1991

pMOS소자의 $p^{+}$게이트 전극으로 다결정실리콘과 비정질실리콘을 사용하여 고온의 열처리 공정에 따른 붕소이온의 침투현상을 high frequency C-V plot, Constant Current Stress Test(CCST), Secondary Ion Mass Spectroscopy(SIMS) 및 Transmission Electron Microscopy(TEM)를 이용하여 비교하였다. C-V plot분석 결과 비정질실리콘 게이트가 다결정실리콘 게이트에 비해 flatband전압의 변화가 작게 나타났으며, 게이트 산화막의 절연파괴 전하밀도에서는 60~80% 정도 향상된 값을 나타내었다. 비정질실리콘 게이트는 증착시 비정질로 형성되는 구조로 인한 얇은 이온주입 깊이와 열처리 공정시 다결정실리콘에 비교하여 크게 성장하는 입자 크기 때문에 붕소이온의 침투 경로가 되는 grain boundary를 감소시켜 붕소이온 확산을 억제한 것으로 생각된다. Electron trapping rate와 flatband 전압 변화와의 관계에 대하여 고찰하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• 대한전자공학회논문지SD
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• 제41권8호
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• pp.1-8
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• 2004

두께가 3nm인 게이트 산화막을 사용한 n-MOSFET에 정전압 스트레스를 가하였을 때 관찰되는 SILC 및 soft breakdown 열화 및 이러한 열화가 소자 특성에 미치는 영향에 대해 실험하였다. 열화 현상은 인가되는 게이트 전압의 극성에 따라 그 특성이 다르게 나타났다. 게이트 전압이 (-)일 때 열화는 계면 및 산화막내 전하 결함에 의해 발생되었지만, 게이트 전압이 (＋)일 때는 열화는 주로 계면 결함에 의해 발생되었다. 또한 이러한 결함의 생성은 Si-H 결합의 파괴에 의해 발생할 수 있다는 것을 중수소 열처리 및 추가 수소 열처리 실험으로부터 발견하였다. OFF 전류 및 여러 가지 MOSFET의 전기적 특성의 변화는 관찰된 결함 전하(charge-trapping)의 생성과 직접적인 관련이 있다. 그러므로 실험 결과들로부터 게이트 산화막으로 터널링되는 전자나 정공에 의한 Si 및 O의 결합 파괴가 게이트 산화막 열화의 원인이 된다고 판단된다. 이러한 물리적 해석은 기존의 Anode-Hole Injection 모델과 Hydrogen-Released 모델의 내용을 모두 포함하게 된다.

• 한국전기전자재료학회논문지
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• 제24권12호
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• pp.939-943
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• 2011

In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.71-71
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• 2011

Dye-sensitized solar cells (DSCs) have drawn great academic attention due to their potential as low-cost renewable energy sources. DSCs contain a nanostructured TiO2 photoanode, which is a key-component for high conversion efficiency. Particularly, one-dimensional (1-D) nanostructured photoanodes can enhance the electron transport for the efficient collection to the conducting substrate in competition with the recombination processes. This is because photoelectron colletion is determined by trapping/detrapping events along the site of the electron traps (defects, surface states, grain boundaries, and self-trapping). Therefore, 1-D nanostructured photoanodes are advantageous for the fast electron transport due to their desirable features of greatly reduced intercrystalline contacts with specified directionality. In particular, anodic TiO2 nanotube (NT) electrodes recently have been intensively explored owing to their ideal structure for application in DSCs. Besides the enhanced electron transport properties resulted from the 1-D structure, highly ordered and vertically oriented nanostructure of anodic TiO2 NT can contribute additional merits, such as enhanced electrolyte diffusion, better interfacial contact with viscous electrolytes. First, to confirm the advantages of 1-D nanostructured material for the photoelectron collection, we compared the electron transport and charge recombination characteristics between nanoparticle (NP)- and nanorod (NR)-based photoanodes in DSCs by the stepped light-induced transient measurements of photocurrent and voltage (SLIM-PCV). We confirmed that the electron lifetime of the NR-based photoanode was much longer than that of the NP-based photoanode. In addition, highly ordered and vertically oriented TiO2 NT photoanodes were prepared by electrochemical anodization method. We compared the photovoltaic properties of DSCs utilizing TiO2 NT photoanodes prepared by one-step anodization and two-step anodization. And, to reduce the charge recombination rate, energy barrier layer (ZnO, Al2O3)-coated TiO2 NTs also applied in DSC. Furthermore, we applied the TiO2 NT photoanode in DSCs using a viscous electrolyte, i.e., cobalt bipyridyl redox electrolyte, and confirmed that the pore structure of NT array can enhance the performances of this viscous electrolyte.