• Transactions on Electrical and Electronic Materials
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• 제3권2호
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• pp.28-31
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• 2002

The Cdl-xZnxTe film was fabricated by thermal evaporation for the flat-panel X-ray detector. The stoichimetric ratio and the crystal structure of a polycrystalline Cd$_{1-x}$ Zn$_{x}$Te were investigated by EPMA and XRD, respectively. The leakage current and X-ray sensitivity of the fabricated films were measured to analyze the X-ray response characteristic of Zn in the polycrystalline CdZnTe thin film. The leakage current and the output charge density of Cd$_{0.7}$Zn$_{0.3}$Te thin film were measured to 0.37 nA/cm$^2$ and 260 pc/cm$^2$ at an applied voltage of 2.5 V/${\mu}{\textrm}{m}$, respectively. Experimental results showed that the increase of Zn doping rates in Cd$_{1-x}$ Zn$_{x}$Te detectors reduced the leakage current and improved the signal to noise ratio significantly.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2007년도 춘계학술대회 논문집
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• pp.1650-1655
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• 2007

A lights-out detector, which helps the person in charge of maintenance make a quick judgment in the event of a failure of LED-type traffic lights, was explored/developed and installed/ tested, at Seoul Metro, after they developed a patented pilot product in 2005; and, a product improvement test was conducted to ensure reasonable maintenance of signaling facilities. Having better compatibility with existing circuit in use and displaying stable load current, the device makes the maintenance of lights-out detection and alert easier.

• Journal of the Optical Society of Korea
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• 제13권2호
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• pp.261-266
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• 2009

The angular dispersion-type non-scanning Fabry-Perot was applied to an ethanol-water mixture in order to investigate its acoustic properties such as the sound velocity and the absorption coefficient. The scattered light from the mixture was analyzed by using the charge-coupled-device area detector, which made the measurement time much shorter than that obtained by using the conventional scanning tandem multi-pass Fabry-Perot interferometer. The sound velocity showed a deviation from ultrasonic sound velocities at low temperatures accompanied by the increase in the absorption coefficient, indicating acoustic dispersion due to the coupling between the acoustic waves and some relaxation process. Based on a simplified viscoelastic theory, the temperature dependence of the relaxation time was obtained. The addition of water molecules to ethanol reduced the relaxation time, consistent with dielectric measurements. The present study showed that the angular dispersion-type Fabry-Perot interferometer combined with an area detector could be a very powerful tool in the real-time monitoring of the acoustic properties of condensed matter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• 한국정보전자통신기술학회논문지
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• 제13권1호
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• pp.48-57
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• 2020

Wireless charger, USB type-C 등의 응용에서 사용되는 MCU는 추가 공정 마스크가 작으면서 셀 사이즈가 작은 MTP 메모리가 요구된다. 기존의 double poly EEPROM 셀은 사이즈가 작지만 3~5 장 정도의 추가 공정 마스크가 요구되고, FN 터널링 방식의 single poly EEPROM 셀은 셀 사이즈가 큰 단점이 있다. 본 논문에서는 vertical PIP 커패시터를 사용한 110nm MTP 셀을 제안하였다. 제안된 MTP 셀의 erase 동작은 FG와 EG 사이의 FN 터널링을 이용하였고 프로그램 동작은 CHEI 주입 방식을 사용하므로 MTP 셀 어레이의 PW을 공유하여 MTP 셀 사이즈를 1.09㎛2으로 줄였다. 한편 USB type-C 등의 응용에서 요구되는 MTP 메모리 IP는 2.5V ~ 5.5V의 넓은 전압 범위에서 동작하는 것이 필요하다. 그런데 VPP 전하펌프의 펌핑 전류는 VCC 전압이 최소인 2.5V일 때 가장 낮은 반면, 리플전압은 VCC 전압이 5.5V일 때 크게 나타난다. 그래서 본 논문에서는 VCC detector 회로를 사용하여 ON되는 전하펌프의 개수를 제어하여 VCC가 높아지더라도 펌핑 전류를 최대 474.6㎂로 억제하므로 SPICE 모의실험을 통해 VPP 리플 전압을 0.19V 이내로 줄였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.161-162
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed RFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블록은 Cadence spectre를 이용하여 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.241-244
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• 2003

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In this study, I propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system, interface of external environment. and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, image classification and memory control of using FPGA, control of mouse signal. And finally, fer stable operation of host controller board, uC/OS-II operating system is ported on the board.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1386-1388
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed PFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블락은 Cadence spectre 를 이용하여 검증하였다.

• ETRI Journal
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• 제30권4호
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.